公开(公告)号：US5418176A

公开(公告)日：1995-05-23

申请号：US197748

申请日：1994-02-17

Applicant: Ming-Tzong Yang ,  Cheng-Han Huang ,  Chen-Chiu Hsue

Inventor： Ming-Tzong Yang ,  Cheng-Han Huang ,  Chen-Chiu Hsue

IPC: H01L21/8246

CPC classification number: H01L27/1122

Abstract: A process of fabricating a read only memory device (ROM) wherein the buried N+lines have desirable well defined very narrow widths and are closely spaced. In the process, an insulating layer is deposited on the substrate. Openings for the buried N+lines having vertical sidewalls are formed through the insulating layer. Spacer layers are formed on the vertical sidewalls of the openings. Impurities are implanted through the openings. The insulating layers is removed and the substrate is oxidized to form silicon oxide insulation strips over the buried N+implanted regions. Next, the read only memory (ROM) device is completed by fabricating floating gates and overlying control gates between the buried N+lines interconnected by a conductive lines that are orthogonal to the buried N+buried lines.

Abstract translation: 一种制造只读存储器件（ROM）的工艺，其中掩埋的N +线具有期望的良好定义非常窄的宽度并且紧密间隔开。 在该过程中，绝缘层沉积在衬底上。 通过绝缘层形成具有垂直侧壁的埋入N +线的开口。 间隔层形成在开口的垂直侧壁上。 通过开口植入杂质。 绝缘层被去除并且衬底被氧化以在掩埋的N +注入区域上形成氧化硅绝缘条。 接下来，通过在与埋置的N +掩埋线正交的导线相互连接的掩埋N +线之间制造浮动栅极和覆盖控制栅极来完成只读存储器（ROM）器件。

公开(公告)号：US5698458A

公开(公告)日：1997-12-16

申请号：US680101

申请日：1996-07-15

Applicant: Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Chung-Yuan Lee ,  Ming-Tzong Yang

Inventor： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Chung-Yuan Lee ,  Ming-Tzong Yang

IPC: H01L21/8238 ,  H01L21/265

CPC classification number: H01L21/823892

Abstract: A method of manufacture of a semiconductor device comprises forming a silicon dioxide film upon the surface of said device, forming patterns of silicon nitride upon the surface of said silicon dioxide film, ion implanting ions into said substrate adjacent to at least some of said silicon nitride patterns for well regions of a first polarity, forming a mask over said device, and deeply ion implanting with ions of opposite polarity into well regions of opposite polarity.

Abstract translation: 一种制造半导体器件的方法包括在所述器件的表面上形成二氧化硅膜，在所述二氧化硅膜的表面上形成氮化硅图案，将离子注入所述衬底中，与所述氮化硅中的至少一些相邻 第一极性的阱区的图案，在所述器件上形成掩模，并且将具有相反极性的离子深入离子注入到相反极性的阱区中。

公开(公告)号：US5578857A

公开(公告)日：1996-11-26

申请号：US349432

申请日：1994-12-05

Applicant: Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

Inventor： Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

IPC: H01L21/8246 ,  H01L29/76

CPC classification number: H01L27/1126

Abstract: In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.

Abstract translation: 根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。 特别地，减小字线间距以在垂直于字线的方向上增加单元密度。 本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

公开(公告)号：US5572056A

公开(公告)日：1996-11-05

申请号：US368146

申请日：1994-12-29

Applicant: Chen-Chiu Hsue ,  Ming-Tzong Yang ,  Te-Sun Wu

Inventor： Chen-Chiu Hsue ,  Ming-Tzong Yang ,  Te-Sun Wu

IPC: H01L21/8246 ,  H01L29/76

CPC classification number: H01L27/112

Abstract: A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.

Abstract translation: 通过在衬底上沉积由选自多晶硅和多晶硅化物的材料构成的第一层来形成ROM，通过掩模和蚀刻对第一层进行图案化，在第一层上沉积介电层，并将介电层和第一层图案化成 形成第一导体线的图案，通过介电层形成接触窗口，直到衬底，在器件上沉积由选自多晶硅和多晶硅化物的材料组成的第二层，并形成与由第一导线形成的第一导体线正交的第二导体线 第一层，以及通过第二层离子注入到衬底中，以形成电连接到第二层的第二导体线的接触区域。

公开(公告)号：US5436186A

公开(公告)日：1995-07-25

申请号：US231516

申请日：1994-04-22

Applicant: Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

Inventor： Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

IPC: H01L21/8242

CPC classification number: H01L27/10852

Abstract: A method for fabricating a capacitors having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming an interdigitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.

Abstract translation: 实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。 电容器制造在具有有源器件区域的硅衬底上。 器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。 通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。 去除剩余的多层模具，并且在底部电极上沉​​积高介电常数绝缘体作为电极间电介质。 顶部电容器电极通过沉积掺杂的多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹部，形成交错的鳍状顶部和底部电容器电极并完成动态随机存取存储器（DRAM）单元。

公开(公告)号：US5393233A

公开(公告)日：1995-02-28

申请号：US92190

申请日：1993-07-14

Applicant: Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

Inventor： Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

IPC: H01L21/8246 ,  H01L21/70

CPC classification number: H01L27/1126

Abstract: In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.

Abstract translation: 根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。 特别地，减小字线间距以在垂直于字线的方向上增加单元密度。 本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

公开(公告)号：US5318921A

公开(公告)日：1994-06-07

申请号：US55867

申请日：1993-05-03

Applicant: Chen-Chiu Hsue ,  Ming-Tzong Yang

Inventor： Chen-Chiu Hsue ,  Ming-Tzong Yang

IPC: H01L21/768 ,  H01L21/8246 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/1122 ,  H01L21/768

Abstract: An insulating layer structure is formed over semiconductor device structures in and on a semiconductor substrate. A conductive polysilicon layer covers the insulating layer which is covered by a silicon oxide layer. The oxide layer is now patterned by lithography and etching. This patterning leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines. A uniform thickness silicon nitride layer is deposited over the oxide layer and the exposed polysilicon layer wherein the thickness is the width of the planned spacing. The nitride layer is anisotropically etched to produce sidewall structures having the width of the planned spacing. The exposed polysilicon layer is oxidized. The sidewall structures are removed by etching. The exposed polysilicon layer is anisotropically etched to form closely spaced polysilicon conductor lines. The silicon oxide layers over the polysilicon conductor lines are removed as by etching. N+ ions are implanted into the silicon substrate under the spacing between the polysilicon conductor lines to form bit lines. An insulating layer structure is formed over the bit lines. Processing continues as before to form a second set of polysilicon lines which form the word lines.

Abstract translation: 半导体衬底上半导体器件结构上形成绝缘层结构。 导电多晶硅层覆盖被氧化硅层覆盖的绝缘层。 氧化层现在通过光刻和蚀刻图案化。 该图案在第一指定的多个多晶硅导体线上留下氧化物的第一图案，并且在第二指定的多个多晶硅导体线之间暴露多晶硅层的氧化物加上第一和第二多晶硅导体线之间的预定间隔 多晶硅导线。 在氧化物层和暴露的多晶硅层上沉积均匀的厚度的氮化硅层，其中厚度是预定间距的宽度。 氮化物层被各向异性蚀刻以产生具有预定间隔宽度的侧壁结构。 暴露的多晶硅层被氧化。 通过蚀刻去除侧壁结构。 暴露的多晶硅层被各向异性蚀刻以形成紧密间隔的多晶硅导体线。 通过蚀刻去除多晶硅导体线上的氧化硅层。 在多晶硅导体线之间的间隔处将N +离子注入到硅衬底中以形成位线。 在位线上形成绝缘层结构。 处理如前所述继续形成形成字线的第二组多晶硅线。

公开(公告)号：US5716884A

公开(公告)日：1998-02-10

申请号：US682403

申请日：1996-07-17

Applicant: Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

Inventor： Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

IPC: H01L21/8242

CPC classification number: H01L27/10852

Abstract: A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming inter-digitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.

Abstract translation: 实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。 电容器制造在具有有源器件区域的硅衬底上。 器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。 通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。 去除剩余的多层模具，并且在底部电极上沉​​积高介电常数绝缘体作为电极间电介质。 顶部电容器电极通过沉积掺杂多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹陷，形成数字化的鳍状顶部和底部电容器电极，并完成动态随机存取存储器（DRAM）单元。

公开(公告)号：US5380673A

公开(公告)日：1995-01-10

申请号：US239130

申请日：1994-05-06

Applicant: Ming-Tzong Yang ,  Chen-Chiu Hsue ,  Anchor Chen

Inventor： Ming-Tzong Yang ,  Chen-Chiu Hsue ,  Anchor Chen

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/92

Abstract: A new structure and method for fabricating a stacked capacitor with increased capacitance and which is more manufacturable was accomplished. The stacked capacitor is part of a dynamic random access memory (DRAM) cell for storing charge on the capacitor and together with a field effect transistor (MOSFET) make up the individual DRAM storage cells on a DRAM chip. Fabricating this improved stacked capacitor involves using an additional electrically conducting layer in the polysilicon layer of the bottom electrode. For example, this layer can be composed from materials in the metal nitride group having high conductivity. One preferred choice being titanium nitride (TiN). The bottom electrode is formed by depositing and patterning a thin layer of polysilicon and a thin layer of the electrically conducting layer and then depositing an upper layer of polysilicon from which vertical sidewalls are formed. The conducting layer provides an etch end point for accurately etching to the correct depth. This provided for a repeatable and more manufacturable process. The stacked capacitor is then completed by depositing a high dielectric constant insulator layer over the bottom electrode and forming a top capacitor electrode to complete the stacked capacitor. The bottom electrode contacts one source/drain contacts of the MOSFET and the bit line contacts the other source/drain contact completing the improved DRAM cell.

Abstract translation: 实现了一种用于制造具有增加的电容并且更可制造的层叠电容器的新结构和方法。 堆叠电容器是用于在电容器上存储电荷并与场效应晶体管（MOSFET）一起构成DRAM芯片上的各个DRAM存储单元的动态随机存取存储器（DRAM）单元的一部分。 制造这种改进的堆叠电容器包括在底部电极的多晶硅层中使用附加的导电层。 例如，该层可以由具有高导电性的金属氮化物基团中的材料构成。 一种优选的选择是氮化钛（TiN）。 底部电极通过沉积和图案化多晶硅薄层和导电层的薄层而形成，然后沉积形成垂直侧壁的多晶硅上层。 导电层提供蚀刻终点以准确地蚀刻到正确的深度。 这提供了可重复和更可制造的过程。 然后通过在底部电极上沉​​积高介电常数绝缘体层并形成顶部电容器电极以完成堆叠的电容器来完成叠层电容器。 底部电极接触MOSFET的一个源极/漏极触点，并且位线接触另一个源极/漏极触点，从而完成改进的DRAM单元。

公开(公告)号：US5661047A

公开(公告)日：1997-08-26

申请号：US318213

申请日：1994-10-05

Applicant: Chen-Chiu Hsue ,  Ming-Tzong Yang

Inventor： Chen-Chiu Hsue ,  Ming-Tzong Yang

IPC: H01L21/8229 ,  H01L21/265

CPC classification number: H01L21/8229

Abstract: A method of forming bipolar ROM device on a semiconductor substrate comprises forming a collector region by doping with a dopant of a first polarity, forming an array of common base regions by doping with a dopant of an opposite polarity, forming a plurality of emitter regions selectively in the base regions by doping with a dopant of first polarity and diffusing the dopant into the emitter regions from doped conductors, which conductors are formed as an array of conductors disposed orthogonally relative to the array of common base elements. The conductors are connected to emitter regions traversed thereby and are isolated from other regions by dielectric layers selectively formed over the other regions to prevent diffusion of dopant therethrough to prevent formation of such emitter regions.

Abstract translation: 在半导体衬底上形成双极型ROM器件的方法包括通过掺杂第一极性的掺杂剂形成集电极区域，通过掺杂相反极性的掺杂剂形成公共基极区域阵列，从而选择性地形成多个发射极区域 通过掺杂第一极性的掺杂剂在基极区域中，并且将掺杂剂从掺杂导体扩散到发射极区域，该导体形成为相对于共同基极元件阵列正交配置的导体阵列。 导体连接到由此穿过的发射极区域，并且通过在其它区域上有选择地形成的电介质层与其它区域隔离，以防止掺杂剂扩散通过其中以防止形成这种发射极区域。