公开(公告)号：US20110089888A1

公开(公告)日：2011-04-21

申请号：US12651484

申请日：2010-01-04

申请人： Tung-Cheng Kuo ,  Chun-Ming Chen ,  Huei-Chia Lo ,  Te-Sun Wu

发明人： Tung-Cheng Kuo ,  Chun-Ming Chen ,  Huei-Chia Lo ,  Te-Sun Wu

IPC分类号： H02J7/00

CPC分类号： H02J7/0065

摘要： A notebook computer battery pack device charges an external electrical device and powers a notebook computer. The notebook computer battery pack device includes battery cells for converting chemical energy into direct current power, a first interface connector for transferring the direct current power to a notebook computer, a second interface connector for transferring the direct current power to the external electrical device, battery management circuitry for providing circuit protection, and charging circuitry for charging the external electrical device through the second interface connector.

摘要翻译： 笔记本电脑电池组装置为外部电气设备充电并为笔记本电脑供电。 笔记本电脑电池组装置包括用于将化学能转换为直流电力的电池单元，用于将直流电转移到笔记本计算机的第一接口连接器，用于将直流电力传送到外部电气设备的第二接口连接器 用于提供电路保护的管理电路和用于通过第二接口连接器对外部电气设备充电的充电电路。

公开(公告)号：US07205614B2

公开(公告)日：2007-04-17

申请号：US10707703

申请日：2004-01-06

申请人： Sheng-Tai Young ,  Te-Sun Wu ,  Tsung-Yuan Lee ,  Chih-Kang Chiu

发明人： Sheng-Tai Young ,  Te-Sun Wu ,  Tsung-Yuan Lee ,  Chih-Kang Chiu

IPC分类号： H01L29/76 ,  H01L29/40

CPC分类号： G11C11/5692 ,  G11C17/12 ,  H01L27/112

摘要： A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.

摘要翻译： 高密度只读存储器（ROM）单元安装在用于存储数据的硅衬底上。 ROM单元包括安装在硅衬底上的第二导电类型的第一掺杂区域，安装在第一掺杂区域中的第一导电类型的多个第一重掺杂区域，第二导电类型的第二掺杂区域 安装在硅衬底上，栅极安装在硅衬底的表面上且与第一掺杂区和第二掺杂区相邻。

公开(公告)号：US20050145948A1

公开(公告)日：2005-07-07

申请号：US10707703

申请日：2004-01-06

申请人： Sheng-Tai Young ,  Te-Sun Wu ,  Tsung-Yuan Lee ,  Chih-Kang Chiu

发明人： Sheng-Tai Young ,  Te-Sun Wu ,  Tsung-Yuan Lee ,  Chih-Kang Chiu

IPC分类号： G11C11/56 ,  G11C17/12 ,  H01L27/112 ,  H01L29/76

CPC分类号： G11C11/5692 ,  G11C17/12 ,  H01L27/112

摘要： A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.

摘要翻译： 高密度只读存储器（ROM）单元安装在用于存储数据的硅衬底上。 ROM单元包括安装在硅衬底上的第二导电类型的第一掺杂区域，安装在第一掺杂区域中的第一导电类型的多个第一重掺杂区域，第二导电类型的第二掺杂区域 安装在硅衬底上，栅极安装在硅衬底的表面上且与第一掺杂区和第二掺杂区相邻。

公开(公告)号：US06420859B1

公开(公告)日：2002-07-16

申请号：US09796950

申请日：2001-02-27

申请人： Hui Fang Tsai ,  Chin Shin Yeh ,  Te Sun Wu

发明人： Hui Fang Tsai ,  Chin Shin Yeh ,  Te Sun Wu

IPC分类号： G05F140

CPC分类号： G05F3/242

摘要： A voltage supply control apparatus, suitable for being applied to a low voltage operation device. The voltage supply control apparatus has a high threshold voltage transistor and a low threshold voltage transistor. When the low voltage operation device is not working, the low threshold voltage transistor is cut off, and the voltage drop of a high voltage received from the power source terminal of the low voltage operation device is controlled by the high threshold voltage transistor. In contrast, when the low voltage operation device is working, the operation enable signal output thereby conducts the low threshold voltage transistor to control the voltage drop of the high voltage received from the power source terminal, so that a high potential is obtained.

摘要翻译： 一种电压供给控制装置，适用于低压运转装置。 电压供给控制装置具有高阈值电压晶体管和低阈值电压晶体管。 当低电压操作装置不工作时，低阈值电压晶体管被切断，并且从低电压操作装置的电源端子接收的高电压的电压降由高阈值电压晶体管控制。 相反，当低电压操作装置工作时，由此操作使能信号输出导通低阈值电压晶体管，以控制从电源端子接收的高电压的电压降，从而获得高电位。

公开(公告)号：US5620915A

公开(公告)日：1997-04-15

申请号：US501659

申请日：1995-07-12

申请人： Hsin-Li Chen ,  Te-Sun Wu

发明人： Hsin-Li Chen ,  Te-Sun Wu

IPC分类号： G11C17/12 ,  H01L21/265

CPC分类号： G11C17/126

摘要： The ROM device comprises a number of memory cells each is constructed based on a MOS transistor, the memory cells in the ROM are arranged into a number of rows and a columns. A number of word lines each connects to the gates of each of the MOS transistors of all the memory cells in each of the rows. A number of bit lines each connects to one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the columns. A multiplexer comprises a number of transmitting transistors, each of the transmitting transistors is connected to a corresponding one of the bit lines, forming a current flow path including the transmitting transistor, the connected bit line, and the memory cells correspondingly connected to the bit line. A sense amplifier is coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal. The method for bypassing null-code sections to comprise programing the transmitting transistor in the current flow path into an off status when all memory cells in the column connecting to the bit line of the transmitting transistor is required to contain null code.

摘要翻译： ROM装置包括多个存储单元，每个存储单元均基于MOS晶体管构成，ROM中的存储单元被布置成多行和一列。 多条字线各自连接到每行中的所有存储单元的MOS晶体管的栅极。 多个位线各自连接到每个列中的所有存储单元的每个MOS晶体管的源极/漏极对中的一个。 多路复用器包括多个发射晶体管，每个发射晶体管连接到对应的一个位线，形成包括发射晶体管，连接的位线和对应地连接到位线的存储单元的电流流路 。 感测放大器耦合到多路复用器，用于感测流过其中的电流流路以输出对应的感测输出信号。 当连接到发射晶体管的位线的列中的所有存储单元都需要包含空代码时，用于旁路零代码段以包括将当前流程中的发送晶体管编程为断开状态的方法。

公开(公告)号：US07079433B1

公开(公告)日：2006-07-18

申请号：US09860971

申请日：2001-05-18

申请人： Chih-Hung Chen ,  Te-Sun Wu

发明人： Chih-Hung Chen ,  Te-Sun Wu

IPC分类号： G11C7/00

CPC分类号： G11C29/006 ,  G11C11/41 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5602

摘要： A wafer level burn-in method for static-random access memory. The SRAM memory has a plurality of word lines and a plurality of bit lines. The SRAM memory also has pull up circuits and equalizer circuits connected to various bit lines. All the word lines are switched on for testing any leakage in the gate dielectric layer. A high potential is applied to a bit line of every bit line pairs and a low potential is applied to the other bit line of the bit line pairs. The pull-up circuits and the equalizer circuits are shut down. The current at a steady state is used to judge the normality of an SRAM chip.

摘要翻译： 一种用于静态随机存取存储器的晶片级老化方法。 SRAM存储器具有多个字线和多个位线。 SRAM存储器还具有连接到各种位线的上拉电路和均衡器电路。 所有的字线都被接通以测试栅介质层中的任何泄漏。 对每个位线对的位线施加高电位，并且将低电位施加到位线对的另一位线。 上拉电路和均衡器电路关闭。 稳态下的电流用于判断SRAM芯片的正常状态。

公开(公告)号：US6014018A

公开(公告)日：2000-01-11

申请号：US177205

申请日：1998-10-22

申请人： Te-Sun Wu ,  Hui-Fang Tsai ,  Tsun-Zu Lin

发明人： Te-Sun Wu ,  Hui-Fang Tsai ,  Tsun-Zu Lin

IPC分类号： G05F3/24 ,  G05F1/40

CPC分类号： G05F3/242

摘要： A voltage-reducing device of low power dissipation is provided, including a plurality of transistors, which are self-connected as diode equivalent. These transistors are then cascaded in series in the same direction and coupled to a voltage source. Since every transistor has a threshold voltage, the voltage at the end of the forward-biased cascaded transistors will be lowered than the voltage source so as to provide a reduced voltage source. Furthermore, since the voltage adjustment of the device is based on the threshold voltage, there is hardly any power dissipation. In addition, we can use different threshold voltages from various transistors to provide different combinations of these threshold voltages to obtain the desired voltage drop.

摘要翻译： 提供低功耗的降压装置，包括多个晶体管，它们作为二极管等效自连接。 然后将这些晶体管以相同的方向串联级联并耦合到电压源。 由于每个晶体管都具有阈值电压，所以正向偏置级联晶体管末端的电压将比电压源降低，从而提供一个降低的电压源。 此外，由于器件的电压调整基于阈值电压，因此几乎不存在功率消耗。 此外，我们可以使用不同晶体管的不同阈值电压来提供这些阈值电压的不同组合，以获得所需的电压降。

公开(公告)号：US5939900A

公开(公告)日：1999-08-17

申请号：US775290

申请日：1996-12-31

申请人： Te Sun Wu

发明人： Te Sun Wu

IPC分类号： H03K19/00 ,  H03K19/094 ,  H03K19/20

CPC分类号： H03K19/0027

摘要： An input buffer which is coupled to a direct voltage source and ground, includes at least one CMOS device and an enhancement mode NMOS transistor, receives at least one input signal and provides one output signal. The input buffer makes use of the enhancement mode NMOS transistor to lower the potential difference between the gate terminal and the source terminal of the PMOS transistor of the CMOS device. Thus, the input buffer can lower the turning on degree of the PMOS transistor effectively. Then the PMOS transistor which is considered as a pull-up transistor can lower the degree to which the input buffer is turned on, and maintain the characteristics and functionality of the input buffer.

摘要翻译： 耦合到直流电压源和接地的输入缓冲器包括至少一个CMOS器件和增强型NMOS晶体管，接收至少一个输入信号并提供一个输出信号。 输入缓冲器利用增强型NMOS晶体管来降低CMOS器件的PMOS晶体管的栅极端子和源极端子之间的电位差。 因此，输入缓冲器可以有效地降低PMOS晶体管的导通程度。 那么被认为是上拉晶体管的PMOS晶体管可以降低输入缓冲器导通的程度，并保持输入缓冲器的特性和功能。

公开(公告)号：US5572056A

公开(公告)日：1996-11-05

申请号：US368146

申请日：1994-12-29

申请人： Chen-Chiu Hsue ,  Ming-Tzong Yang ,  Te-Sun Wu

发明人： Chen-Chiu Hsue ,  Ming-Tzong Yang ,  Te-Sun Wu

IPC分类号： H01L21/8246 ,  H01L29/76

CPC分类号： H01L27/112

摘要： A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.

摘要翻译： 通过在衬底上沉积由选自多晶硅和多晶硅化物的材料构成的第一层来形成ROM，通过掩模和蚀刻对第一层进行图案化，在第一层上沉积介电层，并将介电层和第一层图案化成 形成第一导体线的图案，通过介电层形成接触窗口，直到衬底，在器件上沉积由选自多晶硅和多晶硅化物的材料组成的第二层，并形成与由第一导线形成的第一导体线正交的第二导体线 第一层，以及通过第二层离子注入到衬底中，以形成电连接到第二层的第二导体线的接触区域。

公开(公告)号：US20050207568A1

公开(公告)日：2005-09-22

申请号：US10823239

申请日：2004-04-12

申请人： Te-Sun Wu

发明人： Te-Sun Wu

IPC分类号： H04M1/03 ,  H04M1/60 ,  H04R3/02 ,  H04R25/00

CPC分类号： H04R3/02 ,  H04M1/6033 ,  H04R2217/03 ,  H04R2499/11

摘要： A communicating apparatus generating low echo includes an output module, a receiving module and a control unit. The output module directs a remote voice signal outputted from the control unit, so that the remote signal is transmitted along a specific direction within a specific range. The receiving module receives a local signal, and transmits to the control unit thereby. Wherein the remote audio signal transmitted from the output module is excluded from the receiving module, thus echo is lowered significantly and communication quality is enhanced.

摘要翻译： 产生低回波的通信装置包括输出模块，接收模块和控制单元。 输出模块引导从控制单元输出的远程语音信号，使得远程信号沿特定范围内的特定方向发送。 接收模块接收本地信号，由此发送到控制单元。 其中从输出模块发送的远程音频信号从接收模块中排除，从而显着降低了回波，提高了通信质量。