公开(公告)号：US08255853B2

公开(公告)日：2012-08-28

申请号：US12756990

申请日：2010-04-08

申请人： MingYang Wang ,  Sweyyan Shei ,  Hwa Mao

发明人： MingYang Wang ,  Sweyyan Shei ,  Hwa Mao

IPC分类号： G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/3652

摘要： An apparatus for circuit emulation may include a first circuit board, one or more circuit emulation resource on the first circuit board, a first interconnection interface on the first circuit board, and a second interconnection interface on the first circuit board. The first circuit board may include conductive wiring paths. The circuit emulation resource is on the first circuit board and coupled with a portion of the conductive wiring paths, with each circuit emulation resource being configured to emulate a portion of an electronic circuit by receiving input signals and producing output signals in response to the input signals. The first interconnection interface is on the first circuit board and coupled with at least a first portion of the circuit emulation resource, The first interconnection interface may be configured to couple with an interconnection interface of a second circuit board having a second group of conductive wiring paths and having a second group of circuit emulation resources. The second interconnection interface is on the first circuit board and coupled with at least a second portion of the at least one circuit emulation resource. The second interconnection interface may be configured to couple with an interconnection interface of a third circuit board having a third group of conductive wiring paths and having a third group of circuit emulation resources.

摘要翻译： 用于电路仿真的装置可以包括第一电路板，第一电路板上的一个或多个电路仿真资源，第一电路板上的第一互连接口和第一电路板上的第二互连接口。 第一电路板可以包括导电布线路径。 电路仿真资源在第一电路板上并与一部分导电布线路径耦合，每个电路仿真资源被配置为通过接收输入信号并响应输入信号产生输出信号来模拟电子电路的一部分 。 第一互连接口位于第一电路板上并与电路仿真资源的至少第一部分耦合。第一互连接口可以被配置为与具有第二组导电布线路径的第二电路板的互连接口耦合 并具有第二组电路仿真资源。 第二互连接口位于第一电路板上并与至少一个电路仿真资源的至少第二部分耦合。 第二互连接口可以被配置为与具有第三组导电布线路径并具有第三组电路仿真资源的第三电路板的互连接口耦合。

公开(公告)号：US20110251836A1

公开(公告)日：2011-10-13

申请号：US12756990

申请日：2010-04-08

申请人： MingYang Wang ,  Sweyyan Shei ,  Hwa Mao

发明人： MingYang Wang ,  Sweyyan Shei ,  Hwa Mao

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/3652

摘要： An apparatus for circuit emulation may include a first circuit board, one or more circuit emulation resource on the first circuit board, a first interconnection interface on the first circuit board, and a second interconnection interface on the first circuit board. The first circuit board may include conductive wiring paths. The circuit emulation resource is on the first circuit board and coupled with a portion of the conductive wiring paths, with each circuit emulation resource being configured to emulate a portion of an electronic circuit by receiving input signals and producing output signals in response to the input signals. The first interconnection interface is on the first circuit board and coupled with at least a first portion of the circuit emulation resource, The first interconnection interface may be configured to couple with an interconnection interface of a second circuit board having a second group of conductive wiring paths and having a second group of circuit emulation resources. The second interconnection interface is on the first circuit board and coupled with at least a second portion of the at least one circuit emulation resource. The second interconnection interface may be configured to couple with an interconnection interface of a third circuit board having a third group of conductive wiring paths and having a third group of circuit emulation resources.

摘要翻译： 用于电路仿真的装置可以包括第一电路板，第一电路板上的一个或多个电路仿真资源，第一电路板上的第一互连接口和第一电路板上的第二互连接口。 第一电路板可以包括导电布线路径。 电路仿真资源在第一电路板上并与一部分导电布线路径耦合，每个电路仿真资源被配置为通过接收输入信号并响应输入信号产生输出信号来模拟电子电路的一部分 。 第一互连接口位于第一电路板上并与电路仿真资源的至少第一部分耦合。第一互连接口可以被配置为与具有第二组导电布线路径的第二电路板的互连接口耦合 并具有第二组电路仿真资源。 第二互连接口位于第一电路板上并与至少一个电路仿真资源的至少第二部分耦合。 第二互连接口可以被配置为与具有第三组导电布线路径并具有第三组电路仿真资源的第三电路板的互连接口耦合。

公开(公告)号：US20130035925A1

公开(公告)日：2013-02-07

申请号：US13597997

申请日：2012-08-29

申请人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

发明人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC分类号： G06F9/455

CPC分类号： G06F17/5027

摘要： A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

摘要翻译： 用于模拟电路设计的方法包括在仿真界面处接收与来自定制原型板的验证模块相关联的信号值，其可以由至少一个电路板描述文件描述，并且可以包括至少一个现场可编程门 阵列仿真电路设计。 所述方法还可以包括处理，所探测的信号值与被仿真的电路设计的一部分相关联，所述仿真接口能够被配置为向至少所述验证模块提供定时和控制信息，并且可以包括控制器和 存储器件，其中控制器能够被配置为接收探测信号值。 该方法还可以包括存储处理后的信息并将其发送到主机工作站。

公开(公告)号：US08732650B2

公开(公告)日：2014-05-20

申请号：US13597997

申请日：2012-08-29

申请人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

发明人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

摘要翻译： 用于模拟电路设计的方法包括在仿真界面处接收与来自定制原型板的验证模块相关联的信号值，其可以由至少一个电路板描述文件描述，并且可以包括至少一个现场可编程门 阵列仿真电路设计。 所述方法还可以包括处理，所探测的信号值与被仿真的电路设计的一部分相关联，所述仿真接口能够被配置为向至少所述验证模块提供定时和控制信息，并且可以包括控制器和 存储器件，其中控制器能够被配置为接收探测信号值。 该方法还可以包括存储处理后的信息并将其发送到主机工作站。

公开(公告)号：US20130055177A1

公开(公告)日：2013-02-28

申请号：US13596069

申请日：2012-08-28

申请人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

发明人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F2217/14

摘要： User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

摘要翻译： 对用户的RTL设计进行分析和检测，以便保留感兴趣的信号，并在合成后将其置于网络列表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网络列表中，以确保在运行时可以访问信号值。 之后，执行P＆R处理，并分析输出以将信号名称与FPGA中的寄存器（触发器和锁存器）或存储器块位置相关联。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US08739089B2

公开(公告)日：2014-05-27

申请号：US13596069

申请日：2012-08-28

申请人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

发明人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F7/62

CPC分类号： G06F17/5054 ,  G06F2217/14

摘要： User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

摘要翻译： 用户的寄存器传输级别（RTL）设计进行分析和检测，以使感兴趣的信号得以保留，并且可以在合成后位于网表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网表中，以确保在运行时可以访问信号值。 之后，执行位置和路由（P＆R）处理，并分析输出以将信号名称与现场可编程门阵列（FPGA）器件中的寄存器（触发器和锁存器）或存储器块位置相关联。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US08281280B2

公开(公告)日：2012-10-02

申请号：US13025809

申请日：2011-02-11

申请人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

发明人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： Methods and systems for testing a design under verification (DUV), the method including receiving, at an interface, configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the FPGA images contains a respective portion of the DUV, and a respective verification module associated with a respective FPGA device. The method further includes, sending, by the interface, each of the FPGA images to each of the respective FPGA devices associated with each of the respective FPGA images. The method also includes, sending, by the interface, timing and control information to each of the respective verification modules based on runtime control information received from the host workstation. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.

摘要翻译： 用于测试验证设计（DUV）的方法和系统，所述方法包括在接口处接收配置的现场可编程门阵列（FPGA）图像和运行时间控制信息，其中每个FPGA图像包含DUV的相应部分， 以及与相应的FPGA器件相关联的相应的验证模块。 该方法还包括：通过接口将每个FPGA图像发送到与每个相应FPGA图像相关联的每个相应的FPGA器件。 该方法还包括：基于从主机工作站接收的运行时控制信息，通过接口将定时和控制信息发送到各个验证模块。 响应于接收到的定时和控制信息，各个验证模块中的每一个控制各个FPGA器件中的每一个的DUV的各个部分。

公开(公告)号：US20110202894A1

公开(公告)日：2011-08-18

申请号：US13025809

申请日：2011-02-11

申请人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

发明人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027

摘要： Methods and systems for testing a prototype, the method including receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module. The method further includes, sending, using the first interface component, the configured image to a device. A second interface component may be configured to send timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component. In response to receiving the timing and control information from the second interface component, the verification module may control the device and/or monitor the device state of at least a portion of the user design.

摘要翻译： 用于测试原型的方法和系统，所述方法包括在第一接口部件处接收与代表用户设计的至少一部分的配置图像相关联的配置参数和相关联的验证模块。 该方法还包括：使用第一接口组件将配置的图像发送到设备。 第二接口部件可以被配置为基于从第一接口部件接收到的配置图像和运行时间控制信息中的至少一个来向定时模块发送定时和控制信息。 响应于从第二接口部件接收定时和控制信息，验证模块可以控制设备和/或监视用户设计的至少一部分的设备状态。