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    Phase-locked loop having dynamically adjustable up/down pulse widths
    1.
    发明授权
    Phase-locked loop having dynamically adjustable up/down pulse widths 有权
    锁相环具有动态可调节的上/下脉冲宽度

    公开(公告)号：US07404099B2

    公开(公告)日：2008-07-22

    申请号：US10918301

    申请日：2004-08-13

    申请人： Mingwei Huang ,  Keng L. Wong ,  Raymond (Hon-Mo) Law ,  Chi-Yeu Chao

    发明人： Mingwei Huang ,  Keng L. Wong ,  Raymond (Hon-Mo) Law ,  Chi-Yeu Chao

    IPC分类号： G06F1/00 ,  G06F1/12 ,  G06F1/04

    CPC分类号： H03L7/0891 ,  H03L7/10

    摘要： According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a frequency acquisition stage, a narrow pulse width for the phase-frequency detector control signal when the PLL is in a phase capture stage, and a wide pulse width of the phase-frequency detector control signal when the PLL is in a lock stage.

    摘要翻译： 根据本发明的实施例，锁相环（PLL）可以包括当PLL处于频率采集级时为相位 - 频率检测器控制信号选择宽脉冲宽度的电路，用于相位的窄脉冲宽度 当PLL处于锁相阶段时，PLL处于相位捕获级中的频率检测器控制信号，以及相位 - 频率检测器控制信号的宽脉冲宽度。

    Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
    3.
    发明授权
    Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock 有权
    将具有与系统时钟的可选择的相位差的I / O缓冲器与与系统时钟同步的远程I / O缓冲器进行时钟

    公开(公告)号：US06748549B1

    公开(公告)日：2004-06-08

    申请号：US09604049

    申请日：2000-06-26

    申请人： Chi-Yeu Chao ,  Chee How Lim ,  Keng L. Wong ,  Songmin Kim ,  Gregory F. Taylor

    发明人： Chi-Yeu Chao ,  Chee How Lim ,  Keng L. Wong ,  Songmin Kim ,  Gregory F. Taylor

    IPC分类号： G06F104

    CPC分类号： G01R31/31937

    摘要： Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit. The third delay circuit enables input and output data transmissions from the integrated circuit to be clocked, in effect, out of phase with the I/O clock generated by phase adjustment circuit.

    摘要翻译： 输入/输出（I / O）时钟相位调整电路，用于集成电路芯片的I / O缓冲电路。 在一个实施例中，集成电路芯片包括耦合以接收系统时钟的相位调整电路。 相位调整电路产生I / O时钟，I / O时钟由系统中用于I / O数据传输的集成电路芯片的I / O缓冲电路接收。 相位调整电路包括锁相环（PLL）电路，其被耦合以通过第一延迟电路接收系统时钟。 由PLL电路产生的I / O时钟通过PLL电路的反馈时钟输入端的第二延迟电路接收。 第一和第二延迟电路用于控制PLL电路相对于系统时钟产生的I / O时钟的相位。 在一个实施例中，第三延迟电路包括在集成电路的I / O缓冲电路的I / O数据路径中。 第三延迟电路使得来自集成电路的输入和输出数据传输被实时地与由相位调整电路产生的I / O时钟异相。

    Phase-locked loop having dynamically adjustable up/down pulse widths
    4.
    发明申请
    Phase-locked loop having dynamically adjustable up/down pulse widths 有权
    锁相环具有动态可调的上/下脉冲宽度

    公开(公告)号：US20060034403A1

    公开(公告)日：2006-02-16

    申请号：US10918301

    申请日：2004-08-13

    申请人： Mingwei Huang ,  Keng Wong ,  Raymond Law ,  Chi-Yeu Chao

    发明人： Mingwei Huang ,  Keng Wong ,  Raymond Law ,  Chi-Yeu Chao

    IPC分类号： H04L7/00

    CPC分类号： H03L7/0891 ,  H03L7/10

    摘要： According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a frequency acquisition stage, a narrow pulse width for the phase-frequency detector control signal when the PLL is in a phase capture stage, and a wide pulse width of the phase-frequency detector control signal when the PLL is in a lock stage.

    摘要翻译： 根据本发明的实施例，锁相环（PLL）可以包括当PLL处于频率采集级时为相位 - 频率检测器控制信号选择宽脉冲宽度的电路，用于相位的窄脉冲宽度 当PLL处于锁相阶段时，PLL处于相位捕获级中的频率检测器控制信号，以及相位 - 频率检测器控制信号的宽脉冲宽度。

    Input circuit with switched reference signals
    5.
    发明授权
    Input circuit with switched reference signals 有权
    具有开关参考信号的输入电路

    公开(公告)号：US06781428B2

    公开(公告)日：2004-08-24

    申请号：US09894188

    申请日：2001-06-27

    申请人： Chi-Yeu Chao ,  Gregory F. Taylor

    发明人： Chi-Yeu Chao ,  Gregory F. Taylor

    IPC分类号： H03K3037

    CPC分类号： H03K3/3565

    摘要： An input circuit includes a comparator circuit and a multi-reference circuit. The input circuit receives an input signal and generates an output signal as a function of the input signal and a reference signal received from the multi-reference circuit. The comparator circuit detects a crossing of the input signal relative to the reference signal and causes a corresponding transition of the output signal. In response to the transition of the output signal, the multi-reference circuit provides a different reference signal to the comparator circuit. The reference signals provided by the multi-reference circuit are selected to create hysteresis in the operation of the input circuit.

    摘要翻译： 输入电路包括比较器电路和多参考电路。 输入电路接收输入信号，并产生作为输入信号和从多参考电路接收的参考信号的函数的输出信号。 比较器电路检测输入信号相对于参考信号的交叉，并引起输出信号的相应转变。 响应于输出信号的转变，多参考电路向比较器电路提供不同的参考信号。 选择由多参考电路提供的参考信号以在输入电路的操作中产生滞后。

    I/O device testing method and apparatus
    7.
    发明授权
    I/O device testing method and apparatus 有权
    I / O设备测试方法和设备

    公开(公告)号：US06671847B1

    公开(公告)日：2003-12-30

    申请号：US09709000

    申请日：2000-11-08

    申请人： Chi-Yeu Chao ,  Tawfik R. Arabi ,  Thomas D. Barrett ,  Gregory F. Taylor

    发明人： Chi-Yeu Chao ,  Tawfik R. Arabi ,  Thomas D. Barrett ,  Gregory F. Taylor

    IPC分类号： G06F1100

    CPC分类号： G11C29/1201 ,  G01R31/31715 ,  G01R31/31716

    摘要： An integrated circuit includes circuitry to test input/output (I/O) devices. Test data is provided to a loopback circuit that drives data through the output buffer to the pad, and back onto the integrated circuit through the input buffer. Separate clock signals, with varying phase, are generated for input synchronous elements and output synchronous elements. The phase, and the relative time delay between the separate clocks, changes as an external clock is varied. The external clock is varied to verify the performance parameters of the I/O devices. Each I/O device includes a shift register that can be coupled to the other buffers in a chain, or can be configured to be in a loop.

    摘要翻译： 集成电路包括用于测试输入/输出（I / O）设备的电路。 测试数据被提供给环回电路，其通过输出缓冲器将数据驱动到焊盘，并通过输入缓冲器返回到集成电路。 为输入同步元件和输出同步元件生成具有不同相位的独立时钟信号。 相位以及单独时钟之间的相对时间延迟随着外部时钟的变化而变化。 改变外部时钟来验证I / O设备的性能参数。 每个I / O设备包括移位寄存器，其可以耦合到链中的其他缓冲器，或者可以被配置为处于循环中。

    Input circuit with non-delayed time blanking
    8.
    发明授权
    Input circuit with non-delayed time blanking 失效

    公开(公告)号：US06552570B2

    公开(公告)日：2003-04-22

    申请号：US09894187

    申请日：2001-06-27

    申请人： Gregory F. Taylor ,  Chi-Yeu Chao

    发明人： Gregory F. Taylor ,  Chi-Yeu Chao

    IPC分类号： H03K3356

    CPC分类号： H03K5/1252

    摘要： An input circuit that receives an input signal and generates an output signal as a function of the input signal includes a latching circuit and a time blanking circuit. The latching circuit detects a transition of the input signal and causes a corresponding transition of the output signal. The time blanking circuit prevents the output signal from transitioning again for a predetermined period. This period begins with essentially no delay from the transition of the output signal, which can reduce the input circuit's sensitivity to high frequency noise that may be present on transitions of the input signal.