公开(公告)号：US10924098B2

公开(公告)日：2021-02-16

申请号：US16606196

申请日：2017-04-18

申请人： MINIMA PROCESSOR OY

发明人： Matthew Turnquist ,  Ari Paasio

IPC分类号： H03K5/1534 ,  H03K3/0233 ,  H03K3/037 ,  H03K19/003

摘要： A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.

公开(公告)号：US10469084B2

公开(公告)日：2019-11-05

申请号：US15630665

申请日：2017-06-22

申请人： Minima Processor Oy

发明人： Ari Paasio ,  Lauri Koskinen ,  Matthew Turnquist

IPC分类号： H03L5/00 ,  H03K19/0185 ,  H03K3/356 ,  H03K19/00 ,  H03K19/096

摘要： A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.

公开(公告)号：US20170373691A1

公开(公告)日：2017-12-28

申请号：US15630665

申请日：2017-06-22

申请人： Minima Processor OY

发明人： Ari Paasio ,  Lauri Koskinen ,  Matthew Turnquist

IPC分类号： H03K19/0185 ,  H03K3/356

CPC分类号： H03K19/0185 ,  H03K3/356113 ,  H03K3/356121 ,  H03K3/356191 ,  H03K19/0013 ,  H03K19/018521 ,  H03K19/018585 ,  H03K19/0963

摘要： A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.