公开(公告)号：US10924098B2

公开(公告)日：2021-02-16

申请号：US16606196

申请日：2017-04-18

申请人： MINIMA PROCESSOR OY

发明人： Matthew Turnquist ,  Ari Paasio

IPC分类号： H03K5/1534 ,  H03K3/0233 ,  H03K3/037 ,  H03K19/003

摘要： A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.

公开(公告)号：US10469084B2

公开(公告)日：2019-11-05

申请号：US15630665

申请日：2017-06-22

申请人： Minima Processor Oy

发明人： Ari Paasio ,  Lauri Koskinen ,  Matthew Turnquist

IPC分类号： H03L5/00 ,  H03K19/0185 ,  H03K3/356 ,  H03K19/00 ,  H03K19/096

摘要： A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.

公开(公告)号：US20170373691A1

公开(公告)日：2017-12-28

申请号：US15630665

申请日：2017-06-22

申请人： Minima Processor OY

发明人： Ari Paasio ,  Lauri Koskinen ,  Matthew Turnquist

IPC分类号： H03K19/0185 ,  H03K3/356

CPC分类号： H03K19/0185 ,  H03K3/356113 ,  H03K3/356121 ,  H03K3/356191 ,  H03K19/0013 ,  H03K19/018521 ,  H03K19/018585 ,  H03K19/0963

摘要： A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.

公开(公告)号：US11953970B2

公开(公告)日：2024-04-09

申请号：US17425001

申请日：2019-01-23

申请人： Minima Processor Oy

发明人： Matthew Turnquist ,  Navneet Gupta ,  Lauri Koskinen ,  Tuomas Hollman

IPC分类号： G06F1/00 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/30 ,  H03K19/00

CPC分类号： G06F1/3296 ,  G06F1/3206 ,  G06F11/3072 ,  H03K19/0008

摘要： A controllable voltage source (902) is coupled to a microelectronic circuit (901) for providing an operating voltage. Said microelectronic circuit (901) is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit (502) comprises a data input coupled to an output of a preceding first logic unit (501). The microelectronic circuit (901) responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (502). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.

公开(公告)号：US10114442B2

公开(公告)日：2018-10-30

申请号：US15381170

申请日：2016-12-16

申请人： Minima Processor Oy

发明人： Matthew Turnquist ,  Lauri Koskinen ,  Markus Hiienkari ,  Jani Mäkipää

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/08

摘要： A control system for controlling an operating voltage of an electronic device is presented. The electronic device includes a timing event detector responsive to timing events, such as errors, related to operation of the electronic device. The control system includes a controller for decreasing the operating voltage when the rate of timing events is below a target level and for increasing the operating voltage when the rate of timing events exceeds the target level to search for a threshold voltage that is the smallest operating voltage at which the rate of timing events is substantially at the target level. The control system further includes a controllable clock signal generator for producing a clock signal for operating the electronic device so that the clock frequency is according to an increasing function of the operating voltage. Thus, it is possible to find a voltage-frequency operating point where the energy consumption is minimized.