-
1.发明授权Apparatus for convolution picture processing using delay and intermediate storage 失效用于使用延迟和中间存储进行卷积图像处理的装置
公开(公告)号：US4945496A
公开(公告)日：1990-07-31
申请号：US130240
申请日：1987-11-25
申请人： Mitsuo Kurakake , Shoichi Otsuka , Yutaka Muraoka
发明人： Mitsuo Kurakake , Shoichi Otsuka , Yutaka Muraoka
CPC分类号： G06T5/20 , G06F17/153
摘要： A picture processing apparatus uses coefficient matrix data to perform convolution processing on a time-sharing basis with regard to each item of pixel data of a frame memory (3) which stores plural items of pixel data. When such processing is being performed, the results of addition from the adder (5) are delayed a predetermined period of time by delay device (7), thereby assuring that intermediate processing results may be written in the buffer (9) with certainty. At the same time, a read-out address of the buffer (9) is revised by an amount equivalent to the delay in the write timing, thereby making it possible to speed up the time-sharing convolution processing.
-
2.发明授权Picture processing apparatus including data conversion table for performing convolutional processing 失效图像处理装置，包括执行流水处理的数据转换表
公开(公告)号：US5063525A
公开(公告)日：1991-11-05
申请号：US549237
申请日：1990-07-09
申请人： Mitsuo Kurakake , Shoichi Otsuka , Yutaka Muraoka
发明人： Mitsuo Kurakake , Shoichi Otsuka , Yutaka Muraoka
摘要： A picture processing apparatus inputs window data (W) to look-up tables (TBL) in which operators (G or F) to be applied to pixel data (x) are stored in correlation to the locations of the pixel data. By switching between the operators (G or F) contained in the look-up tables (TBL), window processing corresponding to a data address (i,j) is performed on input pixel data (x.sub.ij).
摘要翻译： 图像处理装置将窗口数据（W）输入到与像素数据的位置相关联地存储要应用于像素数据（x）的运算符（G或F））的查找表（TBL）。 通过在查找表（TBL）中包含的运算符（G或F）之间切换，对输入像素数据（xij）执行对应于数据地址（i，j）的窗口处理。
-
公开(公告)号：US4890100A
公开(公告)日：1989-12-26
申请号：US102562
申请日：1987-09-01
申请人： Mitsuo Kurakake , Shoichi Otsuka , Yutaka Muraoka
发明人： Mitsuo Kurakake , Shoichi Otsuka , Yutaka Muraoka
IPC分类号： G11C11/401 , G06F12/00 , G06T11/40 , G09G5/36 , G09G5/393
CPC分类号： G09G5/393
摘要： The present invention is directed to a picture processing apparatus for painting a picture memory of a CRT display unit or similar apparatus by paint data. In accordance with this picture processing apparatus, a dual-port memory (4) is used as a frame buffer for storing picture information. In order to store paint information in a memory cell array (7), the information is internally transferred from predetermined storage circuit (9) via a data register (8) having a serial input function. The number of times the dual-port memory (4) is accessed from the processor (1) is greatly reduced so that the burden on the processor (1) can be alleviated. It is also possible to shorten the time required for the paint information to be stored in the memory cell array (7).
-
公开(公告)号：US4811098A
公开(公告)日：1989-03-07
申请号：US167853
申请日：1988-01-27
申请人： Mitsuo Kurakake , Shoichi Otsuka , Yutaka Muraoka
发明人： Mitsuo Kurakake , Shoichi Otsuka , Yutaka Muraoka
摘要： In a picture processing apparatus, a front porch time (FP) conforming to a picture signal from a particular picture input unit (2) is stored beforehand in a register (R) by a host computer (8). When the picture input unit (2) outputs a horizontal synchronizing signal (HSYNC), the front porch time (FP) from issuance of the horizontal synchronizing signal (HSYNC) until the beginning of a significant picture information interval (PCPD) is calculated by referring to the register (R) and counting down the value from the register. The picture information is then introduced into a picture memory (6) from the calculated beginning of the significant picture information interval (PCPD). The picture processing apparatus may be used for a variety of different picture input units, as the host computer stores the front porch time corresponding to the particular picture input unit to be used in the register (R) prior to picture processing.
-
公开(公告)号：US5237656A
公开(公告)日：1993-08-17
申请号：US478745
申请日：1990-02-12
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： An image processing apparatus is constructed by providing in parallel a plurality of dyadic look-up tables (10, 20) to which plural items of image data (I1, I2) read out of respective image memories (40, 50) are inputted. The dyadic look-up tables output data corresponding to a prescribed function, and provide this data to an image arithmetic (30) unit, which executes an operation corresponding to the prescribed function.
摘要翻译： PCT No.PCT / JP87 / 00270 Sec。 371日期1987年12月17日第 102（e）1987年12月17日PCT PCT 1987年4月30日PCT公布。 公开号WO87 / 06741 日期：1987年11月5日。一种图像处理装置是通过并行提供多个二次查找表（10,20）构成的，多个图像数据（I1，I2）从各个图像存储器读出 ，50）。 二次查找表输出与规定功能相对应的数据，并将该数据提供给执行与规定功能相对应的操作的图像运算（30）单元。
-
公开(公告)号：US4949282A
公开(公告)日：1990-08-14
申请号：US221250
申请日：1988-06-28
申请人： Yutaka Muraoka
发明人： Yutaka Muraoka
IPC分类号： G06T7/60
CPC分类号： G06T7/606
摘要： A device for calculating the moments of image data has a plurality of image frame memories. The device has an image frame memory (12) for storing original image data, an image frame memory (13) for storing processed data, and image frame memories (13, 14) for storing weight data in includes an adder(7) for processing the data stored in these memories, a multiplier (6) for multiplying the data in the image frame memories, and an accumulator (8) for temporarily storing calculating results. These memories and the arithmetic units such as the adder (7) and other serve to calculate the zero-order, primary, and secondary moments of image data.
摘要翻译： 图像帧存储器（12）存储用于存储处理数据的原始图像数据存储器（13）和用于存储横向和垂直称重数据的存储器（13,14）。 进一步提供一种用于处理存储在存储器中的数据的加法器（7），用于实现存储器之间乘法的乘法器（6）和用于临时存储计算结果的累加器（8）。 通过由存储器和加法器组成的算术单元来计算零级初级和次级图像数据的时刻。
-
公开(公告)号：US6150786A
公开(公告)日：2000-11-21
申请号：US199275
申请日：1998-11-25
申请人： Jiro Kinoshita , Yutaka Muraoka
发明人： Jiro Kinoshita , Yutaka Muraoka
CPC分类号： G05B19/19
摘要： A controller for an industrial machine capable of monitoring a receiving circuit for receiving position information. A receiving circuit and an additional receiving circuit receive the same position information from a detector, and a monitoring circuit monitors a receiving state of the receiving circuit using position information received by the additional receiving circuit. A plurality of receiving circuits may be provided for respectively receiving different position information, and a plurality of additional receiving circuits and a plurality of monitoring circuits may be provided in a manner such that each additional receiving circuit and each monitoring circuit is associated with each receiving circuit. A single additional receiving circuit and a single monitoring circuit may be common to a plurality of receiving circuits.
摘要翻译： 一种用于工业机器的控制器，其能够监视接收电路以接收位置信息。 接收电路和附加接收电路从检测器接收相同的位置信息，并且监视电路使用由附加接收电路接收的位置信息监视接收电路的接收状态。 可以提供多个接收电路来分别接收不同的位置信息，并且可以以每个附加接收电路和每个监视电路与每个接收电路相关联的方式提供多个附加接收电路和多个监视电路 。 单个附加接收电路和单个监控电路可以是多个接收电路的公共的。
-
公开(公告)号：US6147865A
公开(公告)日：2000-11-14
申请号：US269068
申请日：1999-03-18
申请人： Kazuyuki Sasaki , Kazuhiko Hirano , Yutaka Muraoka
发明人： Kazuyuki Sasaki , Kazuhiko Hirano , Yutaka Muraoka
CPC分类号： H05K7/20172
摘要： A casing structure for a numerical control unit in which a cooling fan mounted on a fan cover is electrically connected with a control board attached to a main cover without using cables. A terminal unit connected with wiring of a fan motor is fixed to a fan cover, and a power supply terminal to be directly connected with the terminal unit is fixed to an upper end portion of a main control board The terminal unit is connected with or disconnected from the power supply terminal by attaching or detaching the fan cover to or from a casing body. Since cables are not needed for connection, a casing can be assembled and disassembled easily. Further, since an assembling error due to interference of cables is eliminated, automation of the assembling work can be easily achieved.
摘要翻译： PCT No.PCT / JP98 / 03252 Sec。 371 1999年3月18日 102（e）1999年3月18日PCT PCT 1998年7月18日PCT公布。 出版物WO99 / 04609 日期1999年1月28日用于数字控制单元的壳体结构，其中安装在风扇罩上的冷却风扇与连接到主盖的控制板电连接，而不使用电缆。 与风扇电动机的配线连接的端子单元固定在风扇罩上，与端子单元直接连接的电源端子固定在主控板的上端部。端子单元连接或断开 从电源端子通过将风扇盖安装或拆卸到壳体上。 由于连接不需要电缆，因此可以容易地组装和拆卸外壳。 此外，由于消除了由于电缆的干扰而导致的组装误差，因此可以容易地实现组装工作的自动化。
-
公开(公告)号：US06526324B1
公开(公告)日：2003-02-25
申请号：US09199274
申请日：1998-11-25
申请人： Jiro Kinoshita , Yutaka Muraoka
发明人： Jiro Kinoshita , Yutaka Muraoka
IPC分类号： G05B1302
CPC分类号： G05B19/042 , G05B19/0423
摘要： A controller capable of monitoring a receiving circuit for receiving machine information. Machine information from a machine is received by a plurality of independent systems and the external signals received by the plurality of systems are compared, thereby, a receiving state of the receiving circuit is monitored. The controller includes a plurality of independent receiving units for receiving the external signal and monitoring units for comparing signals received by the plurality of receiving units, to monitor the receiving units based on a result of the comparison.
摘要翻译： 一种能够监视接收电路以接收机器信息的控制器。 来自机器的机器信息由多个独立系统接收，并且由多个系统接收的外部信号进行比较，从而监视接收电路的接收状态。 控制器包括用于接收外部信号的多个独立接收单元和用于比较由多个接收单元接收的信号的监视单元，以基于比较的结果来监视接收单元。
-
公开(公告)号：US4987557A
公开(公告)日：1991-01-22
申请号：US314055
申请日：1989-02-09
申请人： Yutaka Muraoka
发明人： Yutaka Muraoka
CPC分类号： G06F7/5443 , G06T5/20
摘要： A system for calculation of a sum of products is provided in which an inexpensive sum-of-products arithmetic unit is utilized. When n/d processors of a processor array (2) are input with individual data items in a data sequence from a memory (1), the data items are multiplied by set coefficients of n coefficients. An output equal to the sum of the products obtained is added by an adder (3) to a stored value which is read from a corresponding address of an intermediate storage unit (4), and the sum obtained is stored in the intermediate storage unit. The input data is then shifted, and the process described above is again executed. When the process is completed for all the data sequence in the memory (1), the above-described operation is again performed, with the reading of data from the intermediate storage (4) and writing of the output of the adder delayed by n/d cycles and with other coefficients of the n coefficients being set. Such processing of the same data sequence by the processor array (2) is repeated d times, to obtain a desired sum of products.
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.017 秒)
