公开(公告)号：US20070194364A1

公开(公告)日：2007-08-23

申请号：US11785808

申请日：2007-04-20

申请人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

发明人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/872

摘要： A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.

摘要翻译： 提供具有低电阻和高击穿电压的晶体管和二极管。 当具有长方体形状的窄沟槽的底部填充有通过外延方法生长的半导体时，{0.10}平面在窄沟槽的侧壁处露出。 在窄沟槽的每个侧壁上以恒定速率外延生长半导体; 从而产生其中不存在空隙的填充材料。 填充材料的浓度和宽度被优化。 当填充材料完全耗尽时，这允许位于排水层中的填充材料之间的部分被完全耗尽; 从而能够在漏极层中延伸的耗尽层中建立具有恒定强度的电场。

公开(公告)号：US07855413B2

公开(公告)日：2010-12-21

申请号：US11785808

申请日：2007-04-20

申请人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

发明人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/872

摘要： A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.

摘要翻译： 提供具有低电阻和高击穿电压的晶体管和二极管。 当具有长方体形状的窄沟槽的底部填充有通过外延方法生长的半导体时，{0.10}平面在窄沟槽的侧壁处露出。 在窄沟槽的每个侧壁上以恒定速率外延生长半导体; 从而产生其中不存在空隙的填充材料。 填充材料的浓度和宽度被优化。 当填充材料完全耗尽时，这允许位于排水层中的填充材料之间的部分被完全耗尽; 从而能够在漏极层中延伸的耗尽层中建立具有恒定强度的电场。

公开(公告)号：US07230298B2

公开(公告)日：2007-06-12

申请号：US10197565

申请日：2002-07-18

申请人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

发明人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/872

摘要： A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.

摘要翻译： 提供具有低电阻和高击穿电压的晶体管和二极管。 当具有长方体形状的窄沟槽的底部填充有通过外延方法生长的半导体时，{0.10}平面在窄沟槽的侧壁处露出。 在窄沟槽的每个侧壁上以恒定速率外延生长半导体; 从而产生其中不存在空隙的填充材料。 填充材料的浓度和宽度被优化。 当填充材料完全耗尽时，这允许位于排水层中的填充材料之间的部分被完全耗尽; 从而能够在漏极层中延伸的耗尽层中建立具有恒定强度的电场。

公开(公告)号：US20110220918A1

公开(公告)日：2011-09-15

申请号：US13129890

申请日：2009-10-23

申请人： Akihiko Sugai

发明人： Akihiko Sugai

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/872 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/0495 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606

摘要： A high-performance semiconductor device capable of suppressing a leak current with little electric field concentration, reducing an invalid region in a PN junction region, securing a sufficient area for a Schottky junction region, and achieving efficient and easy manufacturing, in which, in one surface of a semiconductor substrate (1) having a first conduction type made of SiC, a PN junction region (7a) and a Schottky junction region (7b) are provided, in the PN junction region (7a), a convex portion (2a) which has a trapezoidal shape in sectional view and includes a second conduction type layer (2) provided on the semiconductor substrate (1) and a contact layer (3) which is in ohmic contact with the second conduction type layer (2) of the convex portion (2a) are provided, and Schottky electrode (4) covers the side surface of the convex portion (2a) and the contact layer (3), and is provided continuously over the PN junction region (7a) and the Schottky junction region (7b).

摘要翻译： 一种高性能的半导体器件，能够以很小的电场浓度抑制泄漏电流，减少了PN结区域中的无效区域，确保了肖特基结区域的足够的面积，并且实现了高效且易于制造，其中在一个 在PN结区域（7a）中设置具有由SiC制成的第一导电类型的半导体衬底（1）的表面，PN结区域（7a）和肖特基结区域（7b） 其具有截面图的梯形形状，并且包括设置在半导体衬底（1）上的第二导电类型层（2）和与凸部的第二导电类型层（2）欧姆接触的接触层（3） 部分（2a），并且肖特基电极（4）覆盖凸部（2a）和接触层（3）的侧表面，并连续地设置在PN结区域（7a）和肖特基结区域 7b）。

公开(公告)号：US08637872B2

公开(公告)日：2014-01-28

申请号：US13129890

申请日：2009-10-23

申请人： Akihiko Sugai

发明人： Akihiko Sugai

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/872 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/0495 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606

摘要： A high-performance semiconductor device capable of suppressing a leak current with little electric field concentration, reducing an invalid region in a PN junction region, securing a sufficient area for a Schottky junction region, and achieving efficient and easy manufacturing, in which, in one surface of a semiconductor substrate (1) having a first conduction type made of SiC, a PN junction region (7a) and a Schottky junction region (7b) are provided, in the PN junction region (7a), a convex portion (2a) which has a trapezoidal shape in sectional view and includes a second conduction type layer (2) provided on the semiconductor substrate (1) and a contact layer (3) which is in ohmic contact with the second conduction type layer (2) of the convex portion (2a) are provided, and Schottky electrode (4) covers the side surface of the convex portion (2a) and the contact layer (3), and is provided continuously over the PN junction region (7a) and the Schottky junction region (7b).

摘要翻译： 一种高性能的半导体器件，能够以很小的电场浓度抑制泄漏电流，减少了PN结区域中的无效区域，确保了肖特基结区域的足够的面积，并且实现了高效和容易的制造，其中在一个 在PN结区域（7a）中设置具有由SiC制成的第一导电类型的半导体衬底（1）的表面，PN结区域（7a）和肖特基结区域（7b） 其具有截面图的梯形形状，并且包括设置在半导体衬底（1）上的第二导电类型层（2）和与凸部的第二导电类型层（2）欧姆接触的接触层（3） 部分（2a），并且肖特基电极（4）覆盖凸部（2a）和接触层（3）的侧表面，并连续地设置在PN结区域（7a）和肖特基结区域 7b）。

公开(公告)号：US08513674B2

公开(公告)日：2013-08-20

申请号：US13132184

申请日：2009-11-25

申请人： Akihiko Sugai ,  Yasuyuki Sakaguchi

发明人： Akihiko Sugai ,  Yasuyuki Sakaguchi

IPC分类号： H01L31/0312 ,  H01L29/24

CPC分类号： H01L21/0465 ,  H01L21/0485 ,  H01L29/6603 ,  H01L29/872

摘要： A method of manufacturing of a semiconductor device (101) includes: a fine pattern forming step of forming p-type impurity regions (3, 4) and surface ohmic contact electrodes (5) using a stepper, after forming an N-type epitaxial layer (2) on a SiC single-crystal substrate (1); a protective film planarizing step of forming a protective film so as to cover the surface ohmic contact electrodes (5) and performing planarization of the protective film; a substrate thinning step of thinning the SiC single-crystal substrate (1); a backside ohmic contact electrode forming step of forming a backside ohmic contact electrode (7) on the SiC single-crystal substrate (1); a surface Schottky contact electrode forming step of forming a Schottky metal portion (8) connected to the p-type impurity regions (3, 4) and the surface ohmic contact electrodes (5); and a step of forming a surface pad electrode (9) that covers the Schottky metal portion (8).

摘要翻译： 半导体器件（101）的制造方法包括：在形成N型外延层之后，使用步进器形成p型杂质区域（3,3）和表面欧姆接触电极（5）的精细图案形成步骤 （2）在SiC单晶衬底（1）上; 形成保护膜以覆盖表面欧姆接触电极（5）并进行保护膜的平坦化的保护膜平坦化工序; 减薄SiC单晶衬底（1）的衬底稀化步骤; 在SiC单晶衬底（1）上形成背面欧姆接触电极（7）的背面欧姆接触电极形成步骤; 表面肖特基接触电极形成步骤，形成连接到p型杂质区（3,4）和表面欧姆接触电极（5）的肖特基金属部分（8）。 以及形成覆盖所述肖特金属部（8）的表面焊盘电极（9）的工序。

公开(公告)号：US20110233563A1

公开(公告)日：2011-09-29

申请号：US13132184

申请日：2009-11-25

申请人： Akihiko Sugai ,  Yasuyuki Sakaguchi

发明人： Akihiko Sugai ,  Yasuyuki Sakaguchi

IPC分类号： H01L29/161 ,  H01L21/28

CPC分类号： H01L21/0465 ,  H01L21/0485 ,  H01L29/6603 ,  H01L29/872

摘要： A method of manufacturing of a semiconductor device (101) includes: a fine pattern forming step of forming p-type impurity regions (3, 4) and surface ohmic contact electrodes (5) using a stepper, after forming an N-type epitaxial layer (2) on a SiC single-crystal substrate (1); a protective film planarizing step of forming a protective film so as to cover the surface ohmic contact electrodes (5) and performing planarization of the protective film; a substrate thinning step of thinning the SiC single-crystal substrate (1); a backside ohmic contact electrode forming step of forming a backside ohmic contact electrode (7) on the SiC single-crystal substrate (1); a surface Schottky contact electrode forming step of forming a Schottky metal portion (8) connected to the p-type impurity regions (3, 4) and the surface ohmic contact electrodes (5); and a step of forming a surface pad electrode (9) that covers the Schottky metal portion (8).

摘要翻译： 半导体器件（101）的制造方法包括：在形成N型外延层之后，使用步进器形成p型杂质区域（3,3）和表面欧姆接触电极（5）的精细图案形成步骤 （2）在SiC单晶衬底（1）上; 形成保护膜以覆盖表面欧姆接触电极（5）并进行保护膜的平坦化的保护膜平坦化工序; 减薄SiC单晶衬底（1）的衬底稀化步骤; 在SiC单晶衬底（1）上形成背面欧姆接触电极（7）的背面欧姆接触电极形成步骤; 表面肖特基接触电极形成步骤，形成连接到p型杂质区（3,4）和表面欧姆接触电极（5）的肖特基金属部分（8）。 以及形成覆盖所述肖特金属部（8）的表面焊盘电极（9）的工序。