公开(公告)号：US07855413B2

公开(公告)日：2010-12-21

申请号：US11785808

申请日：2007-04-20

申请人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

发明人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/872

摘要： A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.

摘要翻译： 提供具有低电阻和高击穿电压的晶体管和二极管。 当具有长方体形状的窄沟槽的底部填充有通过外延方法生长的半导体时，{0.10}平面在窄沟槽的侧壁处露出。 在窄沟槽的每个侧壁上以恒定速率外延生长半导体; 从而产生其中不存在空隙的填充材料。 填充材料的浓度和宽度被优化。 当填充材料完全耗尽时，这允许位于排水层中的填充材料之间的部分被完全耗尽; 从而能够在漏极层中延伸的耗尽层中建立具有恒定强度的电场。

公开(公告)号：US07230298B2

公开(公告)日：2007-06-12

申请号：US10197565

申请日：2002-07-18

申请人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

发明人： Mizue Kitada ,  Kosuke Oshima ,  Toru Kurosaki ,  Shinji Kunori ,  Akihiko Sugai

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/872

摘要： A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.

摘要翻译： 提供具有低电阻和高击穿电压的晶体管和二极管。 当具有长方体形状的窄沟槽的底部填充有通过外延方法生长的半导体时，{0.10}平面在窄沟槽的侧壁处露出。 在窄沟槽的每个侧壁上以恒定速率外延生长半导体; 从而产生其中不存在空隙的填充材料。 填充材料的浓度和宽度被优化。 当填充材料完全耗尽时，这允许位于排水层中的填充材料之间的部分被完全耗尽; 从而能够在漏极层中延伸的耗尽层中建立具有恒定强度的电场。

公开(公告)号：US07196376B2

公开(公告)日：2007-03-27

申请号：US11097998

申请日：2005-04-04

申请人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido

发明人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811

摘要： An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.

摘要翻译： 活动沟槽填充区域23a保持在有源沟槽22的连接到位于栅极沟槽83下方的嵌入区域24的部分。 有源沟槽填充区域23a连接到源极电极膜58a以具有与源极区域64相同的电位。 当在基极区域32a和导电层12之间施加反向偏压时，在嵌入区域24和导电层12之间也施加反向偏压; 因此耗尽层一起展开并且耐受电压增加。

公开(公告)号：US07135718B2

公开(公告)日：2006-11-14

申请号：US10369101

申请日：2003-02-20

申请人： Mizue Kitada ,  Kosuke Ohsima ,  Shinji Kunori ,  Toru Kurosaki

发明人： Mizue Kitada ,  Kosuke Ohsima ,  Shinji Kunori ,  Toru Kurosaki

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the outermost one reaches these relay diffusion layers, and then the outer guard ring portions. The width of the distance between the guard ring portions is shorter where the relay diffusion layers are provided. For the width of the relay diffusion layers, the depletion layer reaches the outer guard ring portions with a lower voltage than the conventional structure.

公开(公告)号：US20070045726A1

公开(公告)日：2007-03-01

申请号：US11528637

申请日：2006-09-28

申请人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido ,  Masato Mikawa

发明人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido ,  Masato Mikawa

IPC分类号： H01L29/94

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.

摘要翻译： 提供具有高耐压的半导体器件。 活动槽22a包括长而窄的主槽部26和与主槽部的纵向侧面连接的副槽部27以及高度低于底面的第二导电型的埋入区域24 第二导电类型的基底扩散区域32a设置在主槽部分26的底表面上。 在子槽部27中设置有与基底扩散区域32a相接触的第二导电类型的活动沟槽填充区域25。 埋入区域24通过有源沟槽填充区域25与基极扩散区域32a接触。 由于一个栅极沟槽83由一个有源槽22a中的掩埋区域24上方的部分形成，所以栅电极插塞48不分离，这允许电极图案被简化。

公开(公告)号：US20050224848A1

公开(公告)日：2005-10-13

申请号：US11097998

申请日：2005-04-04

申请人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido

发明人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811

摘要： An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.

摘要翻译： 活动沟槽填充区域23a保持在有源沟槽22的连接到位于栅极沟槽83下方的嵌入区域24的部分。 有源沟槽填充区域23a连接到源极电极膜58a以具有与源极区域64相同的电位。 当在基极区域32a和导电层12之间施加反向偏压时，在嵌入区域24和导电层12之间也施加反向偏压; 因此耗尽层一起展开并且耐受电压增加。

公开(公告)号：US06906355B2

公开(公告)日：2005-06-14

申请号：US10677429

申请日：2003-10-03

申请人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

发明人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/12 ,  H01L29/47 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L29/74

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872

摘要： A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.

摘要翻译： 提供了具有均匀填充有半导体填料的保护槽的半导体器件。 矩形环形保护槽的四个角部成直角相交，外部和内部辅助扩散区域均圆形连接到四个角。 由于保护槽不必是圆形的，所以在保护槽内暴露的硅单晶的平面取向可以全部为{100}。 因此，保护​​槽中的外延生长均匀地进行，并且沟槽被填充有无缺陷的防护区域。

公开(公告)号：US06841825B2

公开(公告)日：2005-01-11

申请号：US10449002

申请日：2003-06-02

申请人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

发明人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L27/108

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872

摘要： A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

摘要翻译： 提供了一种提高晶体管耐破坏性的技术。 在本发明的晶体管中，填充区域的高度高于掩埋区域的高度，使得填充区域的耐受电压高于掩埋区域的耐受电压。 因此，由于在有源区域发生雪崩击穿，导致雪崩击穿电流流过具有大面积的有源区域，不会发生电流集中。 结果，增加了抵抗击穿的元件的坚固性。

公开(公告)号：US07365391B2

公开(公告)日：2008-04-29

申请号：US11528637

申请日：2006-09-28

申请人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido ,  Masato Mikawa

发明人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido ,  Masato Mikawa

IPC分类号： H01L31/00

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.

摘要翻译： 提供具有高耐压的半导体器件。 活动槽22a包括长而窄的主槽部26和与主槽部的纵向侧面连接的副槽部27以及高度低于底面的第二导电型的埋入区域24 第二导电类型的基底扩散区域32a设置在主槽部分26的底表面上。 在子槽部27中设置有与基底扩散区域32a相接触的第二导电类型的活动沟槽填充区域25。 埋入区域24通过有源沟槽填充区域25与基极扩散区域32a接触。 由于一个栅极沟槽83由一个有源槽22a中的掩埋区域24上方的部分形成，所以栅电极插塞48不分离，这允许电极图案被简化。

公开(公告)号：US07208375B2

公开(公告)日：2007-04-24

申请号：US10967657

申请日：2004-10-19

申请人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

发明人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872

摘要： A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

摘要翻译： 提供了一种提高晶体管耐破坏性的技术。 在本发明的晶体管中，填充区域的高度高于掩埋区域的高度，使得填充区域的耐受电压高于掩埋区域的耐受电压。 因此，由于在有源区域发生雪崩击穿，导致雪崩击穿电流流过具有大面积的有源区域，不会发生电流集中。 结果，增加了抵抗击穿的元件的坚固性。