Preventing overwriting of shared memory line segments

    公开(公告)号:US11630774B2

    公开(公告)日:2023-04-18

    申请号:US17483945

    申请日:2021-09-24

    Abstract: Techniques are disclosed for preventing overwriting of shared line segments. The techniques include sending a data unit from a first processor to second processor using an augmented hardware cache coherency protocol, the augmented hardware cache coherency protocol being augmented to maintain dirty bits information during an exchange of the data unit within a cache coherency domain. A size of the data unit is a fraction of a size of any shared line of a shared memory, and writing the data unit to a segment of a shared line of a shared memory includes using another protocol, without overwriting another segment of the shared line. The writing is based at least in part on the dirty bits information, and the other protocol does not support hardware coherency and maintains the dirty bits information.

    Secure distributed execution of jobs

    公开(公告)号:US11714897B2

    公开(公告)日:2023-08-01

    申请号:US17406815

    申请日:2021-08-19

    CPC classification number: G06F21/54 G06F9/4403 G06F9/4881 G06F2221/034

    Abstract: A processing unit, where the processing unit one of a group of processing units of a system, includes a processor; and memory including instructions, which when executed by the processor while avoiding interrupting a controller that does not belong to the group of processing units, cause the processor to: perform at least one iteration of the steps of: (a) entering a trusted mode, (b) selecting a selected job to be executed by the processing unit, (c) retrieving access control metadata related to the selected job, (d) entering, by the processing unit, an untrusted mode, (e) executing the selected job by the processing unit while adhering to the access control metadata related to the job, and (f) resetting the processing unit.

    PREVENTING OVERWRITING OF SHARED MEMORY LINE SEGMENTS

    公开(公告)号:US20220100659A1

    公开(公告)日:2022-03-31

    申请号:US17483945

    申请日:2021-09-24

    Abstract: Techniques are disclosed for preventing overwriting of shared line segments. The techniques include sending a data unit from a first processor to second processor using an augmented hardware cache coherency protocol, the augmented hardware cache coherency protocol being augmented to maintain dirty bits information during an exchange of the data unit within a cache coherency domain. A size of the data unit is a fraction of a size of any shared line of a shared memory, and writing the data unit to a segment of a shared line of a shared memory includes using another protocol, without overwriting another segment of the shared line. The writing is based at least in part on the dirty bits information, and the other protocol does not support hardware coherency and maintains the dirty bits information.

    Secure distributed execution of jobs

    公开(公告)号:US12086239B2

    公开(公告)日:2024-09-10

    申请号:US18210794

    申请日:2023-06-16

    CPC classification number: G06F21/54 G06F9/4403 G06F9/4881 G06F2221/034

    Abstract: A processing unit, where the processing unit one of a group of processing units of a system, includes a processor; and memory including instructions, which when executed by the processor while avoiding interrupting a controller that does not belong to the group of processing units, cause the processor to: perform at least one iteration of the steps of: (a) entering a trusted mode, (b) selecting a selected job to be executed by the processing unit, (c) retrieving access control metadata related to the selected job, (d) entering, by the processing unit, an untrusted mode, (e) executing the selected job by the processing unit while adhering to the access control metadata related to the job, and (f) resetting the processing unit.

    SYSTEMS AND METHODS FOR PROCESSING ATOMIC COMMANDS

    公开(公告)号:US20230195506A1

    公开(公告)日:2023-06-22

    申请号:US18110605

    申请日:2023-02-16

    CPC classification number: G06F9/467 G06V20/54

    Abstract: A method for executing atomic commands may include receiving, by an interface of an atomic command execution unit and from a plurality of requestors, a plurality of memory mapped atomic commands. The method may also include executing the plurality of memory mapped atomic commands to provide output values. The method may further include storing, in a first memory unit of the atomic command execution unit, requestor specific information. Different entries of a plurality of entries of the first memory unit may be allocated to different requestors of the plurality of requestors. The method may also include storing, in a second memory unit of the atomic command execution unit, the output values of the plurality of memory mapped atomic commands, and outputting, by the interface and to at least one of the plurality of requestors, at least one indication indicating a completion of at least one of the atomic commands.

Patent Agency Ranking