公开(公告)号：US20070096775A1

公开(公告)日：2007-05-03

申请号：US11286087

申请日：2005-11-22

申请人： Mohamed Elgebaly ,  Khurram Malik ,  Lew Chua-Eoan ,  Seong-Ook Jung

发明人： Mohamed Elgebaly ,  Khurram Malik ,  Lew Chua-Eoan ,  Seong-Ook Jung

IPC分类号： H03B21/00

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Techniques for adaptively scaling voltage for a processing core are described. In one scheme, the logic speed and the wire speed for the processing core are characterized, e.g., using a ring oscillator having multiple signal paths composed of different circuit components. A target clock frequency for the processing core is determined, e.g., based on computational requirements for the core. A replicated critical path is formed based on the characterized logic speed and wire speed and the target clock frequency. This replicated critical path emulates the actual critical path in the processing core and may include different types of circuit components such as logic cells with different threshold voltages, dynamic cells, bit line cells, wires, drivers with different threshold voltages and/or fan-outs, and so on. The supply voltage for the processing core and the replicated critical path is adjusted such that both achieve the desired performance.

摘要翻译： 描述了用于自适应地缩放处理核心的电压的技术。 在一种方案中，处理核心的逻辑速度和线速度的特征在于，例如使用具有由不同电路部件组成的多个信号路径的环形振荡器。 例如，基于对核心的计算要求来确定处理核心的目标时钟频率。 基于特征逻辑速度和线速度和目标时钟频率形成复制关键路径。 该复制的关键路径模拟处理核心中的实际关键路径，并且可以包括不同类型的电路组件，例如具有不同阈值电压的逻辑单元，动态单元，位线单元，电线，具有不同阈值电压的驱动器和/或扇出 ， 等等。 调整处理核心和复制关键路径的电源电压，使得两者都达到期望的性能。

公开(公告)号：US07417482B2

公开(公告)日：2008-08-26

申请号：US11286087

申请日：2005-11-22

申请人： Mohamed Elgebaly ,  Khurram Zaka Malik ,  Lew G. Chua-Eoan ,  Seong-Ook Jung

发明人： Mohamed Elgebaly ,  Khurram Zaka Malik ,  Lew G. Chua-Eoan ,  Seong-Ook Jung

IPC分类号： H03H11/26

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Techniques for adaptively scaling voltage for a processing core are described. In one scheme, the logic speed and the wire speed for the processing core are characterized, e.g., using a ring oscillator having multiple signal paths composed of different circuit components. A target clock frequency for the processing core is determined, e.g., based on computational requirements for the core. A replicated critical path is formed based on the characterized logic speed and wire speed and the target clock frequency. This replicated critical path emulates the actual critical path in the processing core and may include different types of circuit components such as logic cells with different threshold voltages, dynamic cells, bit line cells, wires, drivers with different threshold voltages and/or fan-outs, and so on. The supply voltage for the processing core and the replicated critical path is adjusted such that both achieve the desired performance.

摘要翻译： 描述了用于自适应地缩放处理核心的电压的技术。 在一种方案中，处理核心的逻辑速度和线速度的特征在于，例如使用具有由不同电路部件组成的多个信号路径的环形振荡器。 例如，基于对核心的计算要求来确定处理核心的目标时钟频率。 基于特征逻辑速度和线速度和目标时钟频率形成复制关键路径。 该复制的关键路径模拟处理核心中的实际关键路径，并且可以包括不同类型的电路组件，例如具有不同阈值电压的逻辑单元，动态单元，位线单元，电线，具有不同阈值电压的驱动器和/或扇出 ， 等等。 调整处理核心和复制关键路径的电源电压，使得两者都达到期望的性能。

公开(公告)号：US20070069796A1

公开(公告)日：2007-03-29

申请号：US11239714

申请日：2005-09-29

申请人： Mohamed Elgebaly

发明人： Mohamed Elgebaly

IPC分类号： H03L5/00

CPC分类号： H03K19/018521

摘要： A low-voltage level converter provides level conversion for multiple-supply voltages for very large scale integration (VLSI) systems. Low voltage-level down conversion is achieved at very low voltage operation for on-chip test circuitry for multiple-supply voltage systems. The converter includes an output driver PMOS FET (positive metal-oxide semiconductor field effect transistor) with its well grounded. An output NMOS FET (negative MOS FET) and an extra input pulldown NMOS FET are connected in parallel to the input of the converter. The extra input pulldown NMOS FET provides a negative gate voltage at its drain to the output driver PMOS FET gate. The negative gate voltage and grounded well significantly decrease rise time of the output signal noise pulse of the converter and virtually eliminate a negative spike voltage at the initial transition of the output pulse produced by coupling effect between the input pulse and output pulse due to Miller capacitance effect.

摘要翻译： 低电压电平转换器为大规模集成（VLSI）系统的多电源电压提供电平转换。 对于多电源电压系统的片上测试电路，在非常低的电压操作下实现了低电压电平降低转换。 该转换器包括具有良好接地的输出驱动器PMOS FET（正金属氧化物半导体场效应晶体管）。 输出NMOS FET（负MOS FET）和额外的输入下拉NMOS FET并联连接到转换器的输入端。 额外的输入下拉NMOS FET在其漏极处向输出驱动器PMOS FET栅极提供负栅极电压。 负栅极电压和接地阱显着降低了转换器的输出信号噪声脉冲的上升时间，并且在输入脉冲和输出脉冲之间的耦合效应产生的输出脉冲的初始转变时实际消除了负尖峰电压，这是由于米勒电容 影响。

公开(公告)号：US07944266B2

公开(公告)日：2011-05-17

申请号：US11239714

申请日：2005-09-29

申请人： Mohamed Elgebaly

发明人： Mohamed Elgebaly

IPC分类号： H03L5/00

CPC分类号： H03K19/018521

摘要： A low-voltage level converter provides level conversion for multiple-supply voltages for very large scale integration (VLSI) systems. Low voltage-level down conversion is achieved at very low voltage operation for on-chip test circuitry for multiple-supply voltage systems. The converter includes an output driver PMOS FET (positive metal-oxide semiconductor field effect transistor) with its well grounded. An output NMOS FET (negative MOS FET) and an extra input pulldown NMOS FET are connected in parallel to the input of the converter. The extra input pulldown NMOS FET provides a negative gate voltage at its drain to the output driver PMOS FET gate. The negative gate voltage and grounded well significantly decrease rise time of the output signal noise pulse of the converter and virtually eliminate a negative spike voltage at the initial transition of the output pulse produced by coupling effect between the input pulse and output pulse due to Miller capacitance effect.

摘要翻译： 低电压电平转换器为大规模集成（VLSI）系统的多电源电压提供电平转换。 对于多电源电压系统的片上测试电路，在非常低的电压操作下实现了低电压电平降低转换。 该转换器包括具有良好接地的输出驱动器PMOS FET（正金属氧化物半导体场效应晶体管）。 输出NMOS FET（负MOS FET）和额外的输入下拉NMOS FET并联连接到转换器的输入端。 额外的输入下拉NMOS FET在其漏极处向输出驱动器PMOS FET栅极提供负栅极电压。 负栅极电压和接地阱显着降低了转换器的输出信号噪声脉冲的上升时间，并且在由输入脉冲和输出脉冲之间的耦合效应产生的输出脉冲的初始转变时实际消除了负尖峰电压，这是由于米勒电容 影响。

公开(公告)号：US07583555B2

公开(公告)日：2009-09-01

申请号：US10814935

申请日：2004-03-30

申请人： Inyup Kang ,  Karthikeyan Ethirajan ,  Matthew Levi Severson ,  Mohamed Elgebaly ,  Manoj Sachdev ,  Amr Fahim

发明人： Inyup Kang ,  Karthikeyan Ethirajan ,  Matthew Levi Severson ,  Mohamed Elgebaly ,  Manoj Sachdev ,  Amr Fahim

IPC分类号： G11C7/00 ,  G05F1/40

CPC分类号： G05F1/40 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method and apparatus for voltage regulation uses, in one aspect, worst-case supply voltages specific to the process split of the integrated device at issue. In another aspect, a two-phase voltage regulation system and method identifies the characterization data pertinent to a family of integrated circuit devices in a first phase, and identifies an associated process split of a candidate integrated circuit device in a second phase. The characterization data from the first phase is then used to provide supply voltages that correspond to target frequencies of operation for the candidate device. In another aspect, a hybrid voltage regulator circuit includes an open loop circuit which automatically identifies the process split of the integrated circuit device and allows a regulator to modify supply voltage based on characterization data specific to that process split, and a closed loop circuit which fine-tunes the supply voltage. In one embodiment, the closed-loop circuit includes a critical path replica for providing estimated frequencies of operation necessary for a critical path in the integrated circuit device. A ring oscillator circuit may be used in one embodiment in the critical path and/or in the open loop circuit.

摘要翻译： 一方面，用于电压调节的方法和装置在一个方面使用特定于所讨论的集成器件的工艺分裂的最坏情况的电源电压。 在另一方面，两相电压调节系统和方法识别与第一阶段中的集成电路器件系列相关的特征数据，并且识别在第二阶段中候选集成电路器件的相关联的工艺分组。 然后使用来自第一阶段的表征数据来提供对应于候选设备的目标操作频率的电源电压。 另一方面，混合电压调节器电路包括开环电路，其自动识别集成电路器件的工艺分离，并且允许调节器基于该工艺分离特有的特性数据修改供电电压，以及闭环电路 调节电源电压。 在一个实施例中，闭环电路包括关键路径副本，用于提供集成电路设备中的关键路径所需的估计工作频率。 在一个实施例中，在关键路径和/或开环电路中可以使用环形振荡器电路。