公开(公告)号：US6071783A

公开(公告)日：2000-06-06

申请号：US133353

申请日：1998-08-13

申请人： Mong-Song Liang ,  Jin-Yuan Lee ,  Chue-San Yoo

发明人： Mong-Song Liang ,  Jin-Yuan Lee ,  Chue-San Yoo

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/66636 ,  H01L29/0653 ,  H01L29/41766

摘要： A process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate, via use of a thin silicon oxide layer, has been developed. After formation of a lightly doped source/drain region, an opening is created in the semiconductor substrate, in a region between insulator spacers, on a gate structure, and insulator filled, shallow trench regions, resulting in lightly doped source/drain segments, remaining under the masking insulator spacers. After a thin silicon oxide layer is formed on the exposed silicon surfaces, in the openings, a silicon deposition, and etch back procedures are performed, partially refilling the openings to a depth that still allows the thin silicon oxide layer to be exposed on the sides of the lightly doped source/drain segment. After removal of the exposed portion of the thin silicon oxide layer, and after deposition and etch back of another silicon layer, completely filling the openings, a heavily doped source/drain region is formed in the silicon layers, residing in the openings.

公开(公告)号：US5866451A

公开(公告)日：1999-02-02

申请号：US654498

申请日：1996-05-28

申请人： Chue-San Yoo ,  Mong-Song Liang ,  Jin-Yuan Lee

发明人： Chue-San Yoo ,  Mong-Song Liang ,  Jin-Yuan Lee

IPC分类号： H01L21/8239 ,  H01L21/8244 ,  H01L27/105 ,  H01L27/11 ,  H01L21/8242

CPC分类号： H01L27/11 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1112 ,  H01L27/1116

摘要： An integrated process for forming a 4T SRAM and a mixed-mode capacitor, with logic, on the same integrated circuit, is provided. A semiconductor substrate is provided having field isolation regions, with a gate and gate oxide between the field isolation regions. Polysilicon interconnects are formed over a portion of the field isolation regions, only in a first memory region, and a bottom capacitor plate over a field oxide region in a capacitor region. Active regions are formed in the substrate, adjacent to each gate. Insulating spacers are formed on the sidewalls of the gates, polysilicon interconnects and the floating gate, and later removed from the interconnect. A layer of titanium silicide is formed over the gates and capacitor bottom plate, and also over the polysilicon interconnects and active regions. An interpoly oxide is formed over the semiconductor substrate. An opening is formed in the interpoly oxide over the polysilicon interconnect. A second layer of polysilicon is deposited over the substrate. The second layer of polysilicon is patterned to form a top capacitor plate, and to form a load resistor for the SRAM.

摘要翻译： 提供了在同一集成电路上形成具有逻辑的4T SRAM和混合模式电容器的集成过程。 提供具有场隔离区域的半导体衬底，在场隔离区域之间具有栅极和栅极氧化物。 多晶硅互连形成在场隔离区域的一部分上，仅在第一存储区域中，以及在电容器区域中的场氧化物区域上形成底部电容器板。 有源区形成在衬底中，与每个栅极相邻。 绝缘垫片形成在栅极，多晶硅互连和浮动栅极的侧壁上，并随后从互连中移除。 在栅极和电容器底板上以及多晶硅互连和有源区上形成一层硅化钛。 在半导体衬底上形成一个多晶硅氧化物。 在多晶硅互连上的多晶硅氧化物中形成开口。 第二层多晶硅沉积在衬底上。 图案化第二层多晶硅以形成顶部电容器板，并形成用于SRAM的负载电阻器。

公开(公告)号：US5712201A

公开(公告)日：1998-01-27

申请号：US660306

申请日：1996-06-07

申请人： Jin-Yuan Lee ,  Chue-San Yoo ,  Mong-Song Liang

发明人： Jin-Yuan Lee ,  Chue-San Yoo ,  Mong-Song Liang

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/088

CPC分类号： H01L27/10844 ,  H01L21/823425 ,  H01L27/088

摘要： A semiconductor fabrication process has been developed in which both DRAM and logic device structures are integrated on a single silicon chip. The process features combining process steps for both device types, while using only a single level of polysilicon for both a high capacity DRAM cell, as well as for a CMOS logic cell. The high capacity DRAM cell is composed of an overlying polysilicon storage gate structure, a thin dielectric layer, and an underlying doped semiconductor regions.

摘要翻译： 已经开发了半导体制造工艺，其中DRAM和逻辑器件结构都集成在单个硅芯片上。 该过程的特征是组合了两种器件类型的工艺步骤，同时对于高容量DRAM单元以及CMOS逻辑单元仅使用单层多晶硅。 高容量DRAM单元由上覆多晶硅存储栅结构，薄介电层和下掺杂半导体区构成。

公开(公告)号：US5605853A

公开(公告)日：1997-02-25

申请号：US654131

申请日：1996-05-28

申请人： Chue-San Yoo ,  Mong-Song Liang ,  Jin-Yuan Lee

发明人： Chue-San Yoo ,  Mong-Song Liang ,  Jin-Yuan Lee

IPC分类号： H01L27/105 ,  H01L27/11 ,  H01L21/8247 ,  H01L21/8244

CPC分类号： H01L27/1112 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/11546

摘要： An integrated process for forming a 4T SRAM and a floating gate memory, with logic, on the same integrated circuit, is provided. A semiconductor substrate is provided having field isolation regions, with a gate and gate oxide between the field isolation regions. Polysilicon interconnects are formed over a portion of the field isolation regions, only in a first memory region, and a floating gate over a field oxide region in a second memory region. Active regions are formed in the substrate, adjacent to each gate. Insulating spacers are formed on the sidewalls of the gates, polysilicon interconnects and the floating gate, and later removed from the interconnect. A layer of titanium silicide is formed over the gates, except over the floating gate in the second memory region, and also over the polysilicon interconnects and active regions. An interpoly oxide is formed over the semiconductor substrate. An opening is formed in the interpoly oxide over the polysilicon interconnect. A second layer of polysilicon is deposited over the substrate. The second layer of polysilicon is patterned to form a control gate over the floating gate, and to form a load resistor for the SRAM.

摘要翻译： 提供了一种用于在同一集成电路上形成具有逻辑的4T SRAM和浮动栅极存储器的集成过程。 提供具有场隔离区域的半导体衬底，在场隔离区域之间具有栅极和栅极氧化物。 多晶硅互连形成在场隔离区域的一部分上，仅在第一存储区域中，以及位于第二存储区域中的场氧化物区域上的浮置栅极。 有源区形成在衬底中，与每个栅极相邻。 绝缘垫片形成在栅极，多晶硅互连和浮动栅极的侧壁上，并随后从互连中移除。 在栅极上形成一层硅化钛，除了第二存储区域中的浮置栅极之外以及多晶硅互连和有源区域之外。 在半导体衬底上形成一个多晶硅氧化物。 在多晶硅互连上的多晶硅氧化物中形成开口。 第二层多晶硅沉积在衬底上。 图案化第二层多晶硅以在浮动栅极上形成控制栅极，并形成SRAM的负载电阻。

公开(公告)号：US6093616A

公开(公告)日：2000-07-25

申请号：US75366

申请日：1998-05-11

申请人： Mong-Song Liang ,  Jin-Yuan Lee ,  Chue-San Yoo

发明人： Mong-Song Liang ,  Jin-Yuan Lee ,  Chue-San Yoo

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L28/40

摘要： This method forms a capacitor structure on a semiconductor substrate for providing split voltages for semiconductor circuits by the following steps. Form an active area in the substrate serving as a lower capacitor plate for a bottom capacitor and then form a thin dielectric layer and field oxide regions on the substrate, and cover the dielectric layer with a capacitor plate over the active area to complete the bottom capacitor. Form a thick dielectric layer over the device and a via through the thick dielectric layer to the upper capacitor plate. Form a second lower plate for a top capacitor. Form an inter-layer dielectric layer over the second lower plate. Form an upper capacitor layer over the inter-layer dielectric layer to form a top capacitor with a different capacitance value from the bottom capacitor. The value of the capacitance can be varied by selection of the permittivity and/or thickness of the dielectric layer and by variation of the effective plate area of the top and bottom capacitors.

摘要翻译： 该方法通过以下步骤在半导体基板上形成用于半导体电路的分压的电容器结构。 在用作底部电容器的下电容器板的衬底中形成有源区，然后在衬底上形成薄的电介质层和场氧化物区域，并且在有源区域上用电容器板覆盖电介质层以完成底部电容器 。 在器件上形成厚电介质层，并通过厚电介质层通孔到上电容器板。 形成顶部电容器的第二个下板。 在第二下板上形成层间电介质层。 在层间电介质层上形成上层电容层，形成与底层电容不同的电容值的顶层电容。 可以通过选择介电层的介电常数和/或厚度以及顶部和底部电容器的有效平板面积的变化来改变电容的值。

公开(公告)号：US5900658A

公开(公告)日：1999-05-04

申请号：US950233

申请日：1997-10-14

申请人： Jin-Yuan Lee ,  Chue-San Yoo ,  Mong-Song Liang

发明人： Jin-Yuan Lee ,  Chue-San Yoo ,  Mong-Song Liang

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L7/01

CPC分类号： H01L27/10844 ,  H01L21/823425 ,  H01L27/088

摘要： A semiconductor fabrication process has been developed in which both DRAM and logic device structures are integrated on a single silicon chip. The process features combining process steps for both device types, while using only a single level of polysilicon for both a high capacity DRAM cell, as well as for a CMOS logic cell. The high capacity DRAM cell is composed of an overlying polysilicon storage gate structure, a thin dielectric layer, and an underlying doped semiconductor regions.

摘要翻译： 已经开发了半导体制造工艺，其中DRAM和逻辑器件结构都集成在单个硅芯片上。 该过程的特征是组合了两种器件类型的工艺步骤，同时对于高容量DRAM单元以及CMOS逻辑单元仅使用单层多晶硅。 高容量DRAM单元由上覆多晶硅存储栅结构，薄介电层和下掺杂半导体区构成。

公开(公告)号：US5719079A

公开(公告)日：1998-02-17

申请号：US654467

申请日：1996-05-28

申请人： Chue-San Yoo ,  Mong-Song Liang ,  Jin-Yuan Lee

发明人： Chue-San Yoo ,  Mong-Song Liang ,  Jin-Yuan Lee

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S148/019 ,  Y10S148/02

摘要： A method of forming a local interconnect in an SRAM, simultaneously with the formation of a salicide in logic devices on the same semiconductor substrate, is described. A semiconductor substrate on which MOS (Metal Oxide Semiconductor) transistors have been formed is provided. The transistors are separated by field isolation regions, and each transistor has a gate overlying a gate oxide and has source and drain regions in the substrate. Spacers are provided on the sidewalls of the gates, and some of the field oxide regions in the SRAM have polysilicon interconnects, with sidewall spacers. The sidewall spacers are removed from the polysilicon interconnects. A layer of titanium is deposited over the semiconductor substrate. A salicide is formed over the gates, the source and drain regions, and the polysilicon interconnects, so that the local interconnect is formed connecting the polysilicon interconnects to one of the source regions.

摘要翻译： 描述了在SRAM中形成局部互连的方法，同时在同一半导体衬底上的逻辑器件中形成硅化物。 提供其上形成有MOS（金属氧化物半导体）晶体管的半导体衬底。 晶体管由场隔离区域分离，并且每个晶体管具有覆盖栅极氧化物的栅极，并且在衬底中具有源极和漏极区域。 间隔件设置在栅极的侧壁上，SRAM中的一些场氧化物区域具有多晶硅互连，具有侧壁间隔物。 从多晶硅互连中去除侧壁间隔物。 在半导体衬底上沉积一层钛。 在栅极，源极和漏极区域以及多晶硅互连件之间形成自对准硅化物，使得局部互连形成为将多晶硅互连件连接到源极区域之一。

公开(公告)号：US5858830A

公开(公告)日：1999-01-12

申请号：US873835

申请日：1997-06-12

申请人： Chue-San Yoo ,  Mong-Song Liang

发明人： Chue-San Yoo ,  Mong-Song Liang

IPC分类号： H01L21/762 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76224 ,  H01L27/1052

摘要： A method for forming thick field oxide regions, to be used for isolation in MOSFET memory regions, while also forming insulator filled, narrow trenches, to be used for isolation purposes in MOSFET logic regions, has been developed. The fabrication process features initially creating thick field oxide regions, in the MOSFET memory region, obtained via thermal oxidation procedures, followed by creation of a narrow trench opening, in the MOSFET logic region. An ozone aided, silicon oxide, CVD deposition, is used to fill the narrow trench openings, followed by a selective chemical mechanical polishing procedure, used to remove unwanted regions of silicon oxide layer, creating an insulator filled, narrow trench isolation, in the MOSFET logic region.

摘要翻译： 已经开发了用于在MOSFET存储区域中用于隔离的厚场氧化物区域的方法，同时还形成用于MOSFET逻辑区域中的隔离目的的绝缘体填充的窄沟槽。 制造工艺的特征在于，首先在MOSFET存储器区域中产生厚场氧化物区域，通过热氧化程序获得，然后在MOSFET逻辑区域中形成窄沟槽开口。 使用臭氧辅助，氧化硅，CVD沉积来填充窄沟槽开口，随后进行选择性化学机械抛光程序，用于去除氧化硅层的不需要的区域，在MOSFET中产生绝缘体填充的窄沟槽隔离 逻辑区域。

公开(公告)号：US5372957A

公开(公告)日：1994-12-13

申请号：US94747

申请日：1993-07-22

申请人： Mong-Song Liang ,  Chue-San Yoo ,  Mou-shiung Lin

发明人： Mong-Song Liang ,  Chue-San Yoo ,  Mou-shiung Lin

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A method is described for fabricating a lightly doped drain MOS FET integrated circuit device which is useful for sub-half micron ground rules integrated circuits. A pattern of gate electrode structures is formed upon a semiconductor substrate which structures each includes a gate oxide and a polysilicon layer. A pattern of lightly doped regions in the substrate are formed under the structures by multiple ion implantations. After the ion implantations the lightly doped regions are annealed at a temperature and time to cause a critical and desired dopant diffusion. A dielectric spacer structure is formed upon the sidewalls of each of the structures and over the adjacent portions of the substrate. A pattern of heavily doped regions is formed in the substrate adjacent to the dielectric spacer structure on the sidewalls of the structures and over the adjacent portions of the substrate which form lightly doped drain source/drain structures of an MOS FET device to form said integrated circuit device.

摘要翻译： 描述了一种制造用于半微米基准规则集成电路的轻掺杂漏极MOS FET集成电路器件的方法。 在半导体基板上形成栅电极结构的图案，其结构各自包括栅极氧化物和多晶硅层。 通过多次离子注入在该结构下形成衬底中的轻掺杂区域的图案。 在离子注入之后，轻掺杂区域在温度和时间下退火以引起临界和期望的掺杂剂扩散。 介电间隔物结构形成在每个结构的侧壁和衬底的相邻部分之上。 重叠掺杂区域的图案形成在与该结构的侧壁上的电介质间隔物结构相邻的基板上，并且在衬底的相邻部分之上，形成MOS FET器件的轻掺杂漏极/漏极结构，以形成所述集成电路 设备。

公开(公告)号：US5965927A

公开(公告)日：1999-10-12

申请号：US157513

申请日：1998-09-21

申请人： Jin-Yuan Lee ,  Chue-San Yoo ,  Hsien Wei Chin

发明人： Jin-Yuan Lee ,  Chue-San Yoo ,  Hsien Wei Chin

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  Y10S148/055

摘要： An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers over a fuse is made forming vertical sidewalls which expose portions of the insulation layers. A protective layer is formed over the insulation layer, the sidewalls and fuse thus preventing contaminates from diffusing into the exposed insulation layers. A second opening is made in the protective layer over the fuse link to allow a laser beam to melt the underlying fuse link.

摘要翻译： 提出了在保险丝上的绝缘层的开口上形成保护层的改进的结构和方法。 保护层防止污染物进入保险丝开口中暴露的绝缘层，而不会干扰保险丝的激光修整。 形成穿过熔丝的层的开口形成垂直侧壁，其暴露部分绝缘层。 在绝缘层，侧壁和熔断体上形成保护层，从而防止污染物扩散到暴露的绝缘层中。 在熔断体上方的保护层中形成第二个开口，以允许激光束熔化下面的熔断体。