公开(公告)号：US20130113046A1

公开(公告)日：2013-05-09

申请号：US13618127

申请日：2012-09-14

Applicant: Moojin KIM ,  Jeongyun LEE

Inventor： Moojin KIM ,  Jeongyun LEE

IPC: H01L27/06

CPC classification number: H01L27/0255 ,  H01L27/0629

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor device may include a semiconductor element disposed on a substrate and including an insulating layer and a gate electrode, a doped region having a first conductivity-type on the substrate, a conductive interconnection electrically connected to the gate electrode, and a first contact plug having a second conductivity-type and electrically connecting the conductive interconnection and the doped region to each other and constituting a Zeiler diode by junction with the doped region.

Abstract translation: 提供了半导体器件及其形成方法。 半导体器件可以包括设置在衬底上并包括绝缘层和栅电极的半导体元件，在衬底上具有第一导电类型的掺杂区域，电连接到栅电极的导电互连和第一接触插塞 具有第二导电类型，并且将导电互连和掺杂区彼此电连接并通过与掺杂区结合而构成Zeiler二极管。

公开(公告)号：US20170263711A1

公开(公告)日：2017-09-14

申请号：US15605698

申请日：2017-05-25

Applicant: Jeongyun LEE ,  Kwang-Yong YANG ,  Keomyoung SHIN ,  Jinwook LEE ,  Yongseok LEE

Inventor： Jeongyun LEE ,  Kwang-Yong YANG ,  Keomyoung SHIN ,  Jinwook LEE ,  Yongseok LEE

IPC: H01L29/10 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/1033 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/6656

Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.

公开(公告)号：US20170110542A1

公开(公告)日：2017-04-20

申请号：US15208007

申请日：2016-07-12

Applicant: Jeongyun LEE ,  Kwang-Yong YANG ,  Keomyoung SHIN ,  Jinwook LEE ,  Yongseok LEE

Inventor： Jeongyun LEE ,  Kwang-Yong YANG ,  Keomyoung SHIN ,  Jinwook LEE ,  Yongseok LEE

IPC: H01L29/10 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/1033 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/6656

Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.