公开(公告)号：US20060017102A1

公开(公告)日：2006-01-26

申请号：US11100688

申请日：2005-04-07

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L29/76 ,  H01L21/8232

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.

公开(公告)号：US07875938B2

公开(公告)日：2011-01-25

申请号：US12325824

申请日：2008-12-01

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L29/51

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

摘要翻译： 提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。 在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。 然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。 通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

公开(公告)号：US20090108345A1

公开(公告)日：2009-04-30

申请号：US12325824

申请日：2008-12-01

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L29/78

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

摘要翻译： 提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。 在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。 然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。 通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

公开(公告)号：US07473625B2

公开(公告)日：2009-01-06

申请号：US11100688

申请日：2005-04-07

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L21/3205

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.

摘要翻译： 提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。 在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。 然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。 通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

公开(公告)号：US20070158741A1

公开(公告)日：2007-07-12

申请号：US11684830

申请日：2007-03-12

申请人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Lu ,  Ichen Yang ,  Kuan-Po Chen

发明人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Lu ,  Ichen Yang ,  Kuan-Po Chen

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/78627

摘要： A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

摘要翻译： 提供横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 该方法包括以下步骤：（a）提供第一导电类型的衬底; （b）在所述衬底内形成第二导电类型的阱区，所述阱区具有超陡逆向（SSR）阱分布，其中掺杂浓度随着深度而变化，以便在表面区域中提供较轻的掺杂浓度 所述阱区域比在所述阱区域的所述表面区域以下的区域中的区域大; （c）形成部分覆盖所述阱区并与所述阱区绝缘的栅极层; 以及（d）在所述阱区域中形成源极区域和漏极区域中的一个。 SSR阱区域的存在提供了更轻的表面掺杂，以使得能够在LDMOS器件内获得更高的击穿电压，并且进行较重的次表面掺杂以降低导通电阻。

公开(公告)号：US20060189081A1

公开(公告)日：2006-08-24

申请号：US11063932

申请日：2005-02-23

申请人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Lu ,  Ichen Yang ,  Kuan-Po Chen

发明人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Lu ,  Ichen Yang ,  Kuan-Po Chen

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/78627

摘要： A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

摘要翻译： 提供横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 该方法包括以下步骤：（a）提供第一导电类型的衬底; （b）在所述衬底内形成第二导电类型的阱区，所述阱区具有超陡逆向（SSR）阱分布，其中掺杂浓度随着深度而变化，以便在表面区域中提供较轻的掺杂浓度 所述阱区域比在所述阱区域的所述表面区域以下的区域中的区域大; （c）形成部分覆盖所述阱区并与所述阱区绝缘的栅极层; 以及（d）在所述阱区域中形成源极区域和漏极区域中的一个。 SSR阱区域的存在提供了更轻的表面掺杂，以使得能够在LDMOS器件内获得更高的击穿电压，并且进行较重的次表面掺杂以降低导通电阻。

公开(公告)号：US07192834B2

公开(公告)日：2007-03-20

申请号：US11063932

申请日：2005-02-23

申请人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Liu ,  Ichen Yang ,  Kuan-Po Chen

发明人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Liu ,  Ichen Yang ,  Kuan-Po Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/78627

摘要： A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

摘要翻译： 提供横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 该方法包括以下步骤：（a）提供第一导电类型的衬底; （b）在所述衬底内形成第二导电类型的阱区，所述阱区具有超陡逆向（SSR）阱分布，其中掺杂浓度随着深度而变化，以便在表面区域中提供较轻的掺杂浓度 所述阱区域比在所述阱区域的所述表面区域以下的区域中的区域大; （c）形成部分覆盖所述阱区并与所述阱区绝缘的栅极层; 以及（d）在所述阱区域中形成源极区域和漏极区域中的一个。 SSR阱区域的存在提供了更轻的表面掺杂，以使得能够在LDMOS器件内获得更高的击穿电压，并且进行较重的次表面掺杂以降低导通电阻。

公开(公告)号：US20080205166A1

公开(公告)日：2008-08-28

申请号：US12116688

申请日：2008-05-07

申请人： Chia-Lun Hsu ,  Mu-Yi Liu

发明人： Chia-Lun Hsu ,  Mu-Yi Liu

IPC分类号： G11C16/06

CPC分类号： G11C16/0466

摘要： Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers.

摘要翻译： 描述了制造氮化物捕获EEPROM闪速存储器的方法，其中每个存储器单元使用Si-Fin形成其中源极区和漏极区未被掺杂的氮化物俘获EEPROM闪存单元。 使用与氮化物俘获存储器单元的行中的所选多晶硅栅极的每个相邻多晶硅栅极，以产生用作传输所需电压的源极区域或漏极区域的反转区域，其保存存储器的密度 给定每个存储单元的源区和漏区未被掺杂。 闪存包括与多个Si-Fin层交叉的多个多晶硅层。

公开(公告)号：US07382654B2

公开(公告)日：2008-06-03

申请号：US11394649

申请日：2006-03-31

申请人： Chia-Lun Hsu ,  Mu-Yi Liu

发明人： Chia-Lun Hsu ,  Mu-Yi Liu

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-FIN to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-FIN layers.

摘要翻译： 描述了制造氮化物捕获EEPROM闪速存储器的方法，其中每个存储器单元使用Si-FIN形成氮源捕获EEPROM闪存单元，其中源区和漏区未被掺杂。 使用与氮化物俘获存储器单元的行中的所选多晶硅栅极的每个相邻多晶硅栅极，以产生用作传输所需电压的源极区域或漏极区域的反转区域，其保存存储器的密度 给定每个存储单元的源区和漏区未被掺杂。 闪存包括与多个Si-FIN层交叉的多个多晶硅层。

公开(公告)号：US07471564B2

公开(公告)日：2008-12-30

申请号：US12116688

申请日：2008-05-07

申请人： Chia-Lun Hsu ,  Mu-Yi Liu

发明人： Chia-Lun Hsu ,  Mu-Yi Liu

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers.

摘要翻译： 描述了制造氮化物捕获EEPROM闪速存储器的方法，其中每个存储器单元使用Si-Fin形成其中源极区和漏极区未被掺杂的氮化物俘获EEPROM闪存单元。 使用与氮化物俘获存储器单元的行中的所选多晶硅栅极的每个相邻多晶硅栅极，以产生用作传输所需电压的源极区域或漏极区域的反转区域，其保存存储器的密度 给定每个存储单元的源区和漏区未被掺杂。 闪存包括与多个Si-Fin层交叉的多个多晶硅层。