公开(公告)号：US06961271B2

公开(公告)日：2005-11-01

申请号：US10620022

申请日：2003-07-14

申请人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

发明人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

IPC分类号： G11C11/409 ,  G11C5/06 ,  G11C11/404 ,  G11C11/405 ,  G11C7/00

CPC分类号： G11C11/405 ,  G11C11/404

摘要： A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.

摘要翻译： 存储单元阵列块具有由存储单元对构成的单元存储单元，每个存储单元具有存储单元和补充存储单元。 第二单元存储单元与第一单元存储单元进行交织，第四单元存储单元与第三单元存储单元交错。 第一和第二读出放大器分别设置在阵列块的上方和下方。 第一开关将与第一单元存储单元耦合的位线与第一读出放大器连接，并将与第二单元存储单元耦合的位线与第二读出放大器相连接。 第二开关将与第三单元存储单元耦合的位线与第一读出放大器连接，并将与第四单元存储单元耦合的位线连接到第二读出放大器。 选择的单元存储单元选择性地与读出放大器连接，减少读出放大器的数量。

公开(公告)号：US06967860B2

公开(公告)日：2005-11-22

申请号：US10683663

申请日：2003-10-09

申请人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

发明人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

IPC分类号： G11C11/22 ,  G11C7/22

CPC分类号： G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： A ferroelectric random access memory device including a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

摘要翻译： 一种铁电随机存取存储器件，包括能够响应于地址转换产生脉冲信号的脉冲发生器电路。 芯片使能缓冲电路响应于脉冲信号的第一转换而激活芯片使能标志信号。 行选择器电路响应于地址选择并驱动其中一行。 行选择器电路还产生指示板线选择的标志信号。 响应于写入使能信号的激活，控制电路激活板控制信号，并且响应于脉冲信号的第二转换而使板控制信号无效。 根据板控制信号的激活，所选行的板线被重新激活，并且根据板控制信号的去激活而被去激活。

公开(公告)号：US06594174B2

公开(公告)日：2003-07-15

申请号：US10003528

申请日：2001-10-30

申请人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

发明人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric random access memory device of the present invention includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a linear paraelectric capacitor. Data stored in the ferroelectric capacitor is sensed by activating the word line so as to connect the ferroelectric capacitor to the bit line. The plate line is then activated and simultaneously the reference capacitor is connected to a complementary bit line. After a voltage difference between the bit line and the complementary bit line is detected, the reference capacitor is insulated from the complementary bit line.

公开(公告)号：US06504748B2

公开(公告)日：2003-01-07

申请号：US09931617

申请日：2001-08-16

申请人： Mun-Kyu Choi ,  Byung-Gil Jeon

发明人： Mun-Kyu Choi ,  Byung-Gil Jeon

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A nonvolatile memory device comprises a plate line driving circuit having a hierarchical word line structure. The plate line driving circuit is coupled to plate lines corresponding to a main word line. The plate line driving circuit transmits a plate line drive signal to the plate lines when the main word line is selected, and connects the plate lines to the main word line when the main word line is unselected. Therefore, a floating condition in the plate lines when the main word line is unselected can be prevented.

公开(公告)号：US06407943B1

公开(公告)日：2002-06-18

申请号：US09990120

申请日：2001-11-21

申请人： Mun-Kyu Choi ,  Byung-Gil Jeon

发明人： Mun-Kyu Choi ,  Byung-Gil Jeon

IPC分类号： G11C700

CPC分类号： G11C5/147 ,  G11C11/22

摘要： A reference circuit, which is applied to a ferroelectric random access memory device, includes a polarization state detection circuit having dummy cells with ferroelectric capacitors. The detection circuit checks polarization states of the ferroelectric capacitor in the dummy cells using dumping voltages of different levels, and generates pass/fail signals as a check result. The generated pass/fail signals are decoded, using themselves as selection information for selecting one of reference voltages, of different levels, which are generated from a reference voltage generation circuit. Thus, it is possible to generate an optimal reference voltage, which senses a ferroelectric capacitor polarization state that is changed with time.

公开(公告)号：US06392916B1

公开(公告)日：2002-05-21

申请号：US09675559

申请日：2000-09-29

申请人： Mun-Kyu Choi ,  Byung-Gil Jeon

发明人： Mun-Kyu Choi ,  Byung-Gil Jeon

IPC分类号： G11C1112

CPC分类号： G11C5/147 ,  G11C11/22

摘要： A reference circuit, which is applied to a ferroelectric random access memory device, includes a polarization state detection circuit having dummy cells with ferroelectric capacitors. The detection circuit checks polarization states of the ferroelectric capacitor in the dummy cells using dumping voltages of different levels, and generates pass/fail signals as a check result. The generated pass/fail signals are decoded, using themselves as selection information for selecting one of reference voltages, of different levels, which are generated from a reference voltage generation circuit. Thus, it is possible to generate an optimal reference voltage, which senses a ferroelectric capacitor polarization state that is changed with time.

摘要翻译： 应用于铁电随机存取存储器件的参考电路包括具有铁电电容器的虚设单元的极化状态检测电路。 检测电路使用不同电平的倾销电压来检查虚拟电池中的铁电电容器的极化状态，并生成通过/失败信号作为检查结果。 生成的通过/失败信号被解码，使用它们作为从参考电压产生电路产生的用于选择不同电平的参考电压中的一个的选择信息。 因此，可以产生最佳的参考电压，其感测随时间而变化的铁电电容器极化状态。

公开(公告)号：US06914836B2

公开(公告)日：2005-07-05

申请号：US10295718

申请日：2002-11-15

申请人： Byung-Gil Jeon ,  Mun-Kyu Choi

发明人： Byung-Gil Jeon ,  Mun-Kyu Choi

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C7/062 ,  G11C11/4091

摘要： An integrated circuit memory device can include a memory cell circuit configured to store data and a sense amplifier circuit configured to sense and amplify the stored data provided as a first input to the sense amplifier circuit in comparison to a reference voltage provided as a second input to the sense amplifier circuit. A bit line electrically can be coupled to the memory cell circuit and indirectly electrically coupled to the first input of the sense amplifier circuit and configured to provide the stored data to the sense amplifier circuit. A reference voltage line can also be indirectly electrically coupled to the second input of the sense amplifier circuit and configured to provide the reference voltage to the sense amplifier circuit.

摘要翻译： 集成电路存储器件可以包括被配置为存储数据的存储单元电路和读出放大器电路，该读出放大器电路被配置为与作为第二输入提供的参考电压相比，感测和放大作为读出放大器电路的第一输入提供的存储数据 读出放大器电路。 电位线可以耦合到存储单元电路并间接地电耦合到读出放大器电路的第一输入端，并且被配置为将存储的数据提供给读出放大器电路。 参考电压线还可以间接地电耦合到读出放大器电路的第二输入，并且被配置为向读出放大器电路提供参考电压。

公开(公告)号：US06295223B1

公开(公告)日：2001-09-25

申请号：US09559843

申请日：2000-04-26

申请人： Mun-Kyu Choi ,  Byung-Gil Jeon

发明人： Mun-Kyu Choi ,  Byung-Gil Jeon

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： Disclosed is a ferroelectric random access memory having a reference voltage supplying circuit with a capacitor coupling structure. The reference voltage supplying circuit including a coupling capacitor and switching transistors configured on the basis of the capacitor coupling structure. According to the reference voltage supplying circuit of the present invention, voltages on bit lines coupled to a ferroelectric memory cell and to the reference voltage supplying circuit, respectively, are simultaneously activated. Therefore, a stable sensing margin can be secured even though power noise arises during the read operation.

摘要翻译： 公开了一种具有电容耦合结构的参考电压提供电路的铁电随机存取存储器。 该参考电压提供电路包括耦合电容器和基于电容器耦合结构配置的开关晶体管。 根据本发明的基准电压供给电路，分别与铁电存储器单元和基准电压供给电路相连的位线上的电压同时被激活。 因此，即使在读取操作期间产生功率噪声，也可以确保稳定的感测余量。

公开(公告)号：US07106617B2

公开(公告)日：2006-09-12

申请号：US11029616

申请日：2005-01-05

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

公开(公告)号：US06496426B2

公开(公告)日：2002-12-17

申请号：US09884536

申请日：2001-06-19

申请人： Byung-Gil Jeon ,  Ki-Nam Kim

发明人： Byung-Gil Jeon ,  Ki-Nam Kim

IPC分类号： G11C700

CPC分类号： G11C29/785 ,  G11C29/808

摘要： A redundancy circuit for a semiconductor memory device. The redundancy circuit includes redundancy memory cells and a redundancy word line decoder. The redundancy word line decoder has a fuse circuit that includes fuses and an output signal. The output signal is in one of three states depending on input signals. The fuse circuit controls a cutting of the fuses in accordance with the input signals so as to replace defective normal memory cells with the redundancy memory cells depending on a type of defect experienced by the defective normal memory cells.