公开(公告)号：US06967860B2

公开(公告)日：2005-11-22

申请号：US10683663

申请日：2003-10-09

申请人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

发明人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

IPC分类号： G11C11/22 ,  G11C7/22

CPC分类号： G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： A ferroelectric random access memory device including a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

摘要翻译： 一种铁电随机存取存储器件，包括能够响应于地址转换产生脉冲信号的脉冲发生器电路。 芯片使能缓冲电路响应于脉冲信号的第一转换而激活芯片使能标志信号。 行选择器电路响应于地址选择并驱动其中一行。 行选择器电路还产生指示板线选择的标志信号。 响应于写入使能信号的激活，控制电路激活板控制信号，并且响应于脉冲信号的第二转换而使板控制信号无效。 根据板控制信号的激活，所选行的板线被重新激活，并且根据板控制信号的去激活而被去激活。

公开(公告)号：US06961271B2

公开(公告)日：2005-11-01

申请号：US10620022

申请日：2003-07-14

申请人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

发明人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

IPC分类号： G11C11/409 ,  G11C5/06 ,  G11C11/404 ,  G11C11/405 ,  G11C7/00

CPC分类号： G11C11/405 ,  G11C11/404

摘要： A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.

摘要翻译： 存储单元阵列块具有由存储单元对构成的单元存储单元，每个存储单元具有存储单元和补充存储单元。 第二单元存储单元与第一单元存储单元进行交织，第四单元存储单元与第三单元存储单元交错。 第一和第二读出放大器分别设置在阵列块的上方和下方。 第一开关将与第一单元存储单元耦合的位线与第一读出放大器连接，并将与第二单元存储单元耦合的位线与第二读出放大器相连接。 第二开关将与第三单元存储单元耦合的位线与第一读出放大器连接，并将与第四单元存储单元耦合的位线连接到第二读出放大器。 选择的单元存储单元选择性地与读出放大器连接，减少读出放大器的数量。

公开(公告)号：US06594174B2

公开(公告)日：2003-07-15

申请号：US10003528

申请日：2001-10-30

申请人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

发明人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric random access memory device of the present invention includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a linear paraelectric capacitor. Data stored in the ferroelectric capacitor is sensed by activating the word line so as to connect the ferroelectric capacitor to the bit line. The plate line is then activated and simultaneously the reference capacitor is connected to a complementary bit line. After a voltage difference between the bit line and the complementary bit line is detected, the reference capacitor is insulated from the complementary bit line.

公开(公告)号：US06496426B2

公开(公告)日：2002-12-17

申请号：US09884536

申请日：2001-06-19

申请人： Byung-Gil Jeon ,  Ki-Nam Kim

发明人： Byung-Gil Jeon ,  Ki-Nam Kim

IPC分类号： G11C700

CPC分类号： G11C29/785 ,  G11C29/808

摘要： A redundancy circuit for a semiconductor memory device. The redundancy circuit includes redundancy memory cells and a redundancy word line decoder. The redundancy word line decoder has a fuse circuit that includes fuses and an output signal. The output signal is in one of three states depending on input signals. The fuse circuit controls a cutting of the fuses in accordance with the input signals so as to replace defective normal memory cells with the redundancy memory cells depending on a type of defect experienced by the defective normal memory cells.

公开(公告)号：US20070189056A1

公开(公告)日：2007-08-16

申请号：US11675007

申请日：2007-02-14

申请人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

发明人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/221 ,  G11C11/223

摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

摘要翻译： 堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖 位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层 夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。 铁电存储器件执行随机存取操作并具有高集成度。

公开(公告)号：US07586774B2

公开(公告)日：2009-09-08

申请号：US11675007

申请日：2007-02-14

申请人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

发明人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/221 ,  G11C11/223

摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

摘要翻译： 堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖 位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层 夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。 铁电存储器件执行随机存取操作并具有高集成度。

公开(公告)号：US20130345464A1

公开(公告)日：2013-12-26

申请号：US14003276

申请日：2012-02-22

申请人： Min-Keun Oh ,  Ki-Nam Kim ,  Ki-Hyeong Seo ,  Dae-Gil Kwon

发明人： Min-Keun Oh ,  Ki-Nam Kim ,  Ki-Hyeong Seo ,  Dae-Gil Kwon

IPC分类号： C07F9/09

CPC分类号： C07F9/091

摘要： The present invention relates to I- and II-type crystals of L-α-glyceryl phosphoryl choline, and to a method for preparing same. More particularly, the present invention relates to noble I- and II-type anhydride crystals of L-α-glyceryl phosphoryl choline, which have a higher purity than conventional liquid L-α-glyceryl phosphoryl choline, and one advantage of which is that formulations and dosages of pharmaceuticals are easily modified, and another advantage of which is that the hygroscopicity of the crystals are much lower than that of conventional polymorphic crystals, providing excellent stability during storage. The present invention also relates to a method for preparing the I- and II-type crystals of L-α-glyceryl phosphoryl choline.

摘要翻译： 本发明涉及L-α-甘油磷酰胆碱的I型和II型晶体及其制备方法。 更具体地，本发明涉及具有比常规液体L-α-甘油磷酰胆碱更高纯度的L-α-甘油磷酰胆碱的高级I型和II型酸酐晶体，其优点之一是制剂 并且药物的剂量容易改性，其另一个优点是结晶的吸湿性远低于常规多晶型晶体的吸湿性，在储存期间提供极好的稳定性。 本发明还涉及一种制备L-α-甘油磷酰胆碱的I型和II型晶体的方法。

公开(公告)号：US08026504B2

公开(公告)日：2011-09-27

申请号：US12379814

申请日：2009-03-02

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

IPC分类号： H01L47/00

CPC分类号： H01L27/24 ,  Y10S977/774

摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

摘要翻译： 提供半导体器件及其形成方法。 该方法包括制备半导体衬底。 可以在半导体衬底上依次形成绝缘层。 可以在绝缘层之间形成有源元件。 可以在绝缘层中形成公共节点以电连接到有源元件。 公共节点和有源元件可以二维重复地布置在半导体衬底上。

公开(公告)号：US07888667B2

公开(公告)日：2011-02-15

申请号：US12008125

申请日：2008-01-09

申请人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

发明人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

IPC分类号： H01L47/00 ,  H01L21/00 ,  G11C11/00

CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1683 ,  Y10S438/90

摘要： A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

摘要翻译： 相变存储器件包括设置在基板上的模具层，加热电极，填充绝缘图案和相变材料图案。 加热电极设置在使基板穿过模具层的开口中。 加热电极形成为大致圆筒形，其侧壁共形地设置在开口的下内壁上。 填充绝缘图案填充由加热电极的侧壁围绕的空白区域。 相变材料图案设置在模具层上并向下延伸以填充开口的空的部分。 相变材料图案接触加热电极的侧壁的顶表面。

公开(公告)号：US20100330752A1

公开(公告)日：2010-12-30

申请号：US12842703

申请日：2010-07-23

申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/322 ,  H01L21/336

CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。