公开(公告)号：US07782951B2

公开(公告)日：2010-08-24

申请号：US11126533

申请日：2005-05-11

申请人： Murali Babu Muthukrishnan ,  Arvind Raman ,  Bhavani Gopalakrishna Rao ,  Manish Singhal ,  Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Dileep Kumar Tamia

发明人： Murali Babu Muthukrishnan ,  Arvind Raman ,  Bhavani Gopalakrishna Rao ,  Manish Singhal ,  Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Dileep Kumar Tamia

IPC分类号： H04N7/12

CPC分类号： H04N19/53 ,  H04N5/145

摘要： A motion estimation algorithm finds the best match for a given block or macroblock so that the resulting error signal has very low energy level which is computed, for e.g., by the SAD method. The motion estimation algorithm also provides for an optional sub-pixel level estimation and an inter4v search, and allows for restricting the number of searches for a Frame-frame ME (motion estimation) using Top-Top and Bottom-Bottom field MEs. The algorithm provides for a selective early exit and enables selecting a suitable search area with N candidate points (4 to 8) for starting the search. The search is conducted progressively till a minimum error signal (low energy level signal) is reached. The candidate points for search may be in a diamond shaped configuration, and there may be a plurality of successive diamond configurations, the number of which is configurable. The invention has application in MPEG-4 and H.264 standards.

摘要翻译： 运动估计算法找到给定块或宏块的最佳匹配，使得所得到的误差信号具有非常低的能级，例如通过SAD方法计算。 运动估计算法还提供了可选的子像素级估计和inter4v搜索，并且允许使用Top-Top和Bottom-Bottom-field ME限制对帧帧ME（运动估计）的搜索次数。 该算法提供选择性提前退出，并且使得能够选择具有用于开始搜索的N个候选点（4至8）的合适的搜索区域。 搜索逐渐进行，直到达到最小误差信号（低能级信号）。 用于搜索的候选点可以是菱形配置，并且可以存在多个连续的菱形配置，其数量是可配置的。 本发明适用于MPEG-4和H.264标准。

公开(公告)号：US07720145B2

公开(公告)日：2010-05-18

申请号：US11122928

申请日：2005-05-05

申请人： Murali Babu Muthukrishnan ,  Arvind Raman ,  Bhavani Gopalakrishna Rao ,  Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Dileep Kumar Tamia

发明人： Murali Babu Muthukrishnan ,  Arvind Raman ,  Bhavani Gopalakrishna Rao ,  Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Dileep Kumar Tamia

IPC分类号： H04N7/12

CPC分类号： H04N19/587 ,  H04N19/124 ,  H04N19/132 ,  H04N19/149 ,  H04N19/152 ,  H04N19/176 ,  H04N19/61

摘要： A method for achieving bit rate controlled encoding, e.g., constant bit rate, uses a bit rate control model based on bits allocated per macroblock and based on error in estimating bits consumed in an encoding process in a macroblock. The method computes bits consumed per macroblock as a function of the formed bit rate control model, and allocates bits for the macroblock. To this end, a quadratic (second order) equation is used for the model, which equation might default into a first order equation requiring fewer computations, in the event that no second order solutions exist. In one form, the bit rate control model computes the bit rate to satisfy video buffer verifier (VBV) compliance in accordance with MPEG requirements. The bit rate control model makes allowances for the type of macroblock, i.e., inter, intra or bidirectional, and provides for any frame-skips.

摘要翻译： 用于实现比特率控制编码（例如恒定比特率）的方法使用基于每宏块分配的比特率的比特率控制模型，并且基于在宏块中的编码处理中估计消耗的比特中的误差。 该方法根据形成的比特率控制模型计算每宏块消耗的比特，并为宏块分配比特。 为此，对于模型使用二次（二阶）方程，在不存在二阶解的情况下，该方程可能默认为需要较少计算的一阶方程。 在一种形式中，比特率控制模型根据MPEG要求计算比特率以满足视频缓冲器验证器（VBV）符合性。 比特率控制模型对宏块的类型（即帧间，帧内或双向）提供允许，并提供任何帧跳过。

公开(公告)号：US07634776B2

公开(公告)日：2009-12-15

申请号：US11127687

申请日：2005-05-12

申请人： Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Manish Singhal ,  Dileep Kumar Tamia ,  Dinesh Kumar ,  Aditya Kulkarni ,  Murali Babu Muthukrishnan

发明人： Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Manish Singhal ,  Dileep Kumar Tamia ,  Dinesh Kumar ,  Aditya Kulkarni ,  Murali Babu Muthukrishnan

IPC分类号： G06F9/46 ,  G06F9/30 ,  G06T1/20

CPC分类号： G06F15/7842 ,  H04N19/154 ,  H04N19/436 ,  H04N19/61 ,  H04N19/80

摘要： A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput. The invention also provides an article which is programmed to execute the method.

摘要翻译： 用于设计包括例如多媒体编码/解码的多线程处理操作的方法使用具有多个处理器和可选硬件加速器的架构。 该方法包括以下步骤：识别用于处理输入数据的处理阶段的期望时间序列，包括识别所述处理阶段的相互依赖性; 将每个所述处理鼠标分配给处理器; 惊ering处理以适应相互依存关系; 基于所述分配来选择处理操作以得到提供较低平均处理时间的可能管线的子集; 并且从所述子集中选择一个设计流水线以产生总体时序减少以完成所述处理操作。 本发明提供了一种多线程处理流水线，其可应用于使用DSP和诸如DMA控制器和片上存储器之类的共享资源的片上系统（SoC），以提高吞吐量。 本发明还提供了一种被编程以执行该方法的物品。

公开(公告)号：US20050265454A1

公开(公告)日：2005-12-01

申请号：US11126533

申请日：2005-05-11

申请人： Murali Muthukrishnan ,  Arvind Raman ,  Bhavani Rao ,  Manish Singhal ,  Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Dileep Tamia

发明人： Murali Muthukrishnan ,  Arvind Raman ,  Bhavani Rao ,  Manish Singhal ,  Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Dileep Tamia

IPC分类号： H04N5/14 ,  H04N7/12 ,  H04N7/26

CPC分类号： H04N19/53 ,  H04N5/145

摘要： A motion estimation algorithm finds the best match for a given block or macroblock so that the resulting error signal has very low energy level which is computed, for e.g., by the SAD method. The motion estimation algorithm also provides for an optional sub-pixel level estimation and an inter4v search, and allows for restricting the number of searches for a Frame-frame ME (motion estimation) using Top-Top and Bottom-Bottom field MEs. The algorithm provides for a selective early exit and enables selecting a suitable search area with N candidate points (4 to 8) for starting the search. The search is conducted progressively till a minimum error signal (low energy level signal) is reached. The candidate points for search may be in a diamond shaped configuration, and there may be a plurality of successive diamond configurations, the number of which is configurable. The invention has application in MPEG-4 and H.264 standards.

摘要翻译： 运动估计算法找到给定块或宏块的最佳匹配，使得所得到的误差信号具有非常低的能级，例如通过SAD方法计算。 运动估计算法还提供了可选的子像素级估计和inter4v搜索，并且允许使用Top-Top和Bottom-Bottom-field ME限制对帧帧ME（运动估计）的搜索次数。 该算法提供选择性提前退出，并且使得能够选择具有用于开始搜索的N个候选点（4至8）的合适的搜索区域。 搜索逐渐进行，直到达到最小误差信号（低能级信号）。 用于搜索的候选点可以是菱形配置，并且可以存在多个连续的菱形配置，其数量是可配置的。 本发明适用于MPEG-4和H.264标准。

公开(公告)号：US20050262510A1

公开(公告)日：2005-11-24

申请号：US11127687

申请日：2005-05-12

申请人： Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Manish Singhal ,  Dileep Tamia ,  Dinesh Kumar ,  Aditya Kulkarni ,  Murali Muthukrishnan

发明人： Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Manish Singhal ,  Dileep Tamia ,  Dinesh Kumar ,  Aditya Kulkarni ,  Murali Muthukrishnan

IPC分类号： G06F9/46

CPC分类号： G06F15/7842 ,  H04N19/154 ,  H04N19/436 ,  H04N19/61 ,  H04N19/80

摘要： A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput. The invention also provides an article which is programmed to execute the method.

摘要翻译： 用于设计包括例如多媒体编码/解码的多线程处理操作的方法使用具有多个处理器和可选硬件加速器的架构。 该方法包括以下步骤：识别用于处理输入数据的处理阶段的期望时间序列，包括识别所述处理阶段的相互依赖性; 将每个所述处理鼠标分配给处理器; 惊ering处理以适应相互依存关系; 基于所述分配来选择处理操作以得到提供较低平均处理时间的可能管线的子集; 并且从所述子集中选择一个设计流水线以产生总体时序减少以完成所述处理操作。 本发明提供了一种多线程处理流水线，其可应用于使用DSP和诸如DMA控制器和片上存储器之类的共享资源的片上系统（SoC），以提高吞吐量。 本发明还提供了一种被编程以执行该方法的物品。

公开(公告)号：US20050254578A1

公开(公告)日：2005-11-17

申请号：US11122928

申请日：2005-05-05

申请人： Murali Muthukrinan ,  Arvind Raman ,  Bhavani Rao ,  Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Dileep Tamia

发明人： Murali Muthukrinan ,  Arvind Raman ,  Bhavani Rao ,  Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Dileep Tamia

IPC分类号： H04N7/12 ,  H04N7/26 ,  H04N7/46 ,  H04N7/50

CPC分类号： H04N19/587 ,  H04N19/124 ,  H04N19/132 ,  H04N19/149 ,  H04N19/152 ,  H04N19/176 ,  H04N19/61

摘要： A method for achieving bit rate controlled encoding, e.g., constant bit rate, uses a bit rate control model based on bits allocated per macroblock and based on error in estimating bits consumed in an encoding process in a macroblock. The method computes bits consumed per macroblock as a function of the formed bit rate control model, and allocates bits for the macroblock. To this end, a quadratic (second order) equation is used for the model, which equation might default into a first order equation requiring fewer computations, in the event that no second order solutions exist. In one form, the bit rate control model computes the bit rate to satisfy video buffer verifier (VBV) compliance in accordance with MPEG requirements. The bit rate control model makes allowances for the type of macroblock, i.e., inter, intra or bidirectional, and provides for any frame-skips.

摘要翻译： 用于实现比特率控制编码（例如恒定比特率）的方法使用基于每宏块分配的比特率的比特率控制模型，并且基于在宏块中的编码处理中估计消耗的比特中的误差。 该方法根据形成的比特率控制模型计算每宏块消耗的比特，并为宏块分配比特。 为此，对于模型使用二次（二阶）方程，在不存在二阶解的情况下，该方程可能默认为需要较少计算的一阶方程。 在一种形式中，比特率控制模型根据MPEG要求计算比特率以满足视频缓冲器验证器（VBV）符合性。 比特率控制模型对宏块的类型（即帧间，帧内或双向）提供允许，并提供任何帧跳过。

公开(公告)号：US20050262276A1

公开(公告)日：2005-11-24

申请号：US11126556

申请日：2005-05-11

申请人： Kismat Singh ,  Murali Muthukrishnan ,  Sriram Sethuraman ,  Sankaranarayanan Parameswaran ,  Bhavani Rao

发明人： Kismat Singh ,  Murali Muthukrishnan ,  Sriram Sethuraman ,  Sankaranarayanan Parameswaran ,  Bhavani Rao

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A design method for implementing a high-memory algorithm for motion estimation and compensation uses a low internal memory processor and a DMA engine that interacts with the processor and the algorithm. The DMA takes care of large data transfers from an external memory to the processor internal memory and vice-versa, without using the CPU clock cycles. The design method is scalable and is suited to handle huge bandwidths without slowing down the processor. To prevent the processor from being idle during DMA, the processing is pipelined and staggered so that motion compensation is performed on an earlier block or data that is available, while DMA fetches the reference data for the current block. Several DMAs may be set up under an ISR if necessary. The invention has application in video decoders including those conforming to H.264, VC-1, and MPEG-4 ASP.

摘要翻译： 用于实现用于运动估计和补偿的高存储器算法的设计方法使用与处理器和算法交互的低内部存储器处理器和DMA引擎。 DMA不需要使用CPU时钟周期来处理从外部存储器到处理器内部存储器的大量数据传输，反之亦然。 该设计方法是可扩展的，适合处理巨大的带宽，而不会降低处理器的速度。 为了防止处理器在DMA期间处于空闲状态，处理流水线和交错，以便在较早的块或可用数据上执行运动补偿，而DMA获取当前块的参考数据。 如果需要，可以根据ISR设置几个DMA。 本发明适用于包括符合H.264，VC-1和MPEG-4 ASP的视频解码器。

公开(公告)号：US08428118B2

公开(公告)日：2013-04-23

申请号：US11465129

申请日：2006-08-17

申请人： Sriram Sethuraman ,  Arvind Raman ,  Ashwini Kumar ,  Malavika Bhaskaranand ,  Omkiran Sharma

发明人： Sriram Sethuraman ,  Arvind Raman ,  Ashwini Kumar ,  Malavika Bhaskaranand ,  Omkiran Sharma

IPC分类号： H04N7/12 ,  H04N11/02

CPC分类号： G10L19/173 ,  H04N19/40 ,  H04N19/61

摘要： A method/system of transcoding an MPEG 2/4 bit stream into an H.264 format, handles an input MPEG 2/4 bit stream in a decoder, and identifies certain data in the input bit stream for reuse in the H.264 format; and, reuses the identified data in a re-encoder with assistance from a mapping module in transcoding by converting the input bit stream into an output H.264 format. The identified data includes information at a macrolevel and information at a picture level. The information at the macrolevel might comprise additional stages incorporated in the re-encoder module including a Mapping Process stage, a Sub Pixel Refinement stage, a Mode Selection stage to choose from Intra, Inter or Skip modes, followed by the standard H.264 encoding loop and the Entropy Coding Block. The information at the picture level might include; a) average quantizer of frame, and, b) total bits per frame.

摘要翻译： 将MPEG 2/4比特流转码为H.264格式的方法/系统处理解码器中的输入MPEG 2/4比特流，并且识别输入比特流中的某些数据以在H.264格式中重用 ; 并且通过将输入的比特流转换成输出的H.264格式，通过代码转换中的映射模块的帮助，将识别的数据重新编码在重新编码器中。 所识别的数据包括宏观级的信息和图像级的信息。 宏级别的信息可能包括并入重编码器模块中的附加阶段，包括映射处理阶段，子像素精化阶段，从Intra，Inter或Skip模式中选择的模式选择阶段，随后是标准H.264编码 循环和熵编码块。 图片级别的信息可能包括： a）帧的平均量化器，以及b）每帧的总比特数。

公开(公告)号：US20080043831A1

公开(公告)日：2008-02-21

申请号：US11465129

申请日：2006-08-17

申请人： Sriram Sethuraman ,  Arvind Raman ,  Ashwini Kumar ,  Malavika Bhaskaranand ,  Omkiran Sharma

发明人： Sriram Sethuraman ,  Arvind Raman ,  Ashwini Kumar ,  Malavika Bhaskaranand ,  Omkiran Sharma

IPC分类号： H04B1/66

CPC分类号： G10L19/173 ,  H04N19/40 ,  H04N19/61

摘要： A method/system of transcoding an MPEG 2/4 bit stream into an H.264 format, handles an input MPEG 2/4 bit stream in a decoder, and identifies certain data in the input bit stream for reuse in the H.264 format; and, reuses the identified data in a re-encoder with assistance from a mapping module in transcoding by converting the input bit stream into an output H.264 format. The identified data includes information at a macrolevel and information at a picture level. The information at the macrolevel might comprise additional stages incorporated in the re-encoder module including a Mapping Process stage, a Sub Pixel Refinement stage, a Mode Selection stage to choose from Intra, Inter or Skip modes, followed by the standard H.264 encoding loop and the Entropy Coding Block. The information at the picture level might include; a) average quantizer of frame, and, b) total bits per frame.

摘要翻译： 将MPEG 2/4比特流转码为H.264格式的方法/系统处理解码器中的输入MPEG 2/4比特流，并且识别输入比特流中的某些数据以在H.264格式中重用 ; 并且通过将输入的比特流转换成输出的H.264格式，通过代码转换中的映射模块的帮助，将识别的数据重新编码在重新编码器中。 所识别的数据包括宏观级的信息和图像级的信息。 宏级别的信息可能包括并入重编码器模块中的附加阶段，包括映射处理阶段，子像素精化阶段，从Intra，Inter或Skip模式中选择的模式选择阶段，随后是标准H.264编码 循环和熵编码块。 图片级别的信息可能包括： a）帧的平均量化器，以及b）每帧的总比特数。

公开(公告)号：US20080247469A1

公开(公告)日：2008-10-09

申请号：US11696196

申请日：2007-04-04

申请人： Sarat Chandra Vadapalli ,  Sriram Sethuraman

发明人： Sarat Chandra Vadapalli ,  Sriram Sethuraman

IPC分类号： H04N11/02

CPC分类号： H04N19/00187 ,  H04N19/107 ,  H04N19/15 ,  H04N19/176 ,  H04N19/194 ,  H04N19/61 ,  H04N19/89 ,  H04N19/90

摘要： A method and device for tracking error propagation and refreshing a video stream is provided. The proposed subject matter comprises of an error propagation tracking method that works in the sub-sampled domain to reduce computational cycles and memory bandwidth. Further, the tracking based update of the error propagation metric is done differently for static and non-static regions to avoid unnecessary refresh of static areas. Through suitable thresholding of the metric at a macroblock (MB) level, a set of refresh MBs are selected for each frame. These refresh MBs are coded either as an intra MB or as an inter MB that is predicted from one or more reliable reference frames (—frames that are known to be available at the decoder with negligible errors—). Such inter coding of refresh MBs improves the compression efficiency when compared to pure intra coding of refresh MBs. Further, variants to the threshold selection are presented that result in temporally uniform distribution of the number of refresh MBs and a strict refresh scheme wherein all MBs are guaranteed to be with negligible errors following a packet loss within a committed refresh period. In addition, to using the error propagation metric, spatial connectivity to already chosen refresh MBs is used in the selection of additional refresh MBs within a frame and across frames; this reduces the rate of error propagation due to part of a macroblock predicting from older, erroneous neighboring MBs and in turn requiring more refresh MBs on the average per frame.

摘要翻译： 提供了用于跟踪误差传播和刷新视频流的方法和装置。 提出的主题包括在子采样域中工作的误差传播跟踪方法，以减少计算周期和存储器带宽。 此外，对于静态和非静态区域，错误传播度量的基于跟踪的更新是不同的，以避免不必要的刷新静态区域。 通过对宏块（MB）级别的度量的适当阈值处理，为每个帧选择一组刷新MB。 这些刷新MB被编码为内部MB或作为从一个或多个可靠参考帧（已知在解码器处可用的可忽略错误的帧）预测的帧间MB）。 与刷新MB的纯内部编码相比，刷新MB的这种帧间编码提高了压缩效率。 此外，呈现阈值选择的变体，其导致刷新MB的数量的时间上均匀分布，以及严格刷新方案，其中所有MB在保证的刷新周期内的分组丢失之后被保证具有可忽略的错误。 此外，为了使用误差传播度量，在已经选择的刷新MB的空间连接性被用于选择帧内和跨帧的附加刷新MB; 这降低了由于从旧的错误的相邻MB预测的宏块的一部分而导致的误差传播速率，并且进而需要每帧平均更多的刷新MB。