公开(公告)号：US08810352B2

公开(公告)日：2014-08-19

申请号：US13955505

申请日：2013-07-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tomoya Yokoyama ,  Takako Sato ,  Akihiro Ieda ,  Shigetoshi Hayashi ,  Hirokazu Yazaki

IPC: H01F5/00 ,  H01F27/29 ,  H01L23/12 ,  H01F41/04 ,  H01F17/00 ,  H01F3/14

CPC classification number: H01F27/29 ,  H01F3/14 ,  H01F17/0033 ,  H01F27/292 ,  H01F41/04 ,  H01F41/046 ,  Y10T29/4902

Abstract: In a laminated inductor element, outer electrodes and terminal electrodes are electrically connected by via holes, internal wiring lines, and end surface electrodes. The via holes on an upper surface side are provided immediately under the outer electrodes and in a non-magnetic ferrite layer. The via holes on a lower surface side are provided immediately above the terminal electrodes and in a non-magnetic ferrite layer. Since outermost layers are defined by the non-magnetic ferrite layers, a parasitic inductance is not increased, even if the outermost layers are provided with the via holes. In this case, the internal wiring lines are not routed on a surface of the element. Therefore, there is no complication of a wiring pattern, and it is possible to prevent an increase in a mounting area of the element.

Abstract translation: 在层叠电感器元件中，外部电极和端子电极通过通孔，内部布线和端面电极电连接。 上表面侧的通孔设置在外部电极的正下方和非磁性铁氧体层的下方。 下表面侧的通孔设置在端子电极的正上方和非磁性铁氧体层。 由于最外层由非磁性铁氧体层限定，即使最外层设置有通孔，寄生电感也不会增加。 在这种情况下，内部布线不会在元件的表面上布线。 因此，不存在布线图案的复杂化，可以防止元件的安装面积的增大。