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公开(公告)号：US20200185154A1
公开(公告)日：2020-06-11
申请号：US16793041
申请日：2020-02-18
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideaki TANAKA , Daiki FUKUNAGA , Koji MORIYAMA
Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.
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公开(公告)号：US20190096586A1
公开(公告)日：2019-03-28
申请号：US16199546
申请日：2018-11-26
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideaki TANAKA , Daiki FUKUNAGA , Koji MORIYAMA
CPC classification number: H01G4/30 , H01G4/005 , H01G4/1218 , H01G4/232
Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.
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公开(公告)号：US20180240593A1
公开(公告)日：2018-08-23
申请号：US15902188
申请日：2018-02-22
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yuya TAKAGI , Akira FUJITA , Hideaki TANAKA , Togo MATSUI
CPC classification number: H01G4/012 , H01G4/12 , H01G4/1227 , H01G4/1236 , H01G4/224 , H01G4/232 , H01G4/248 , H01G4/30
Abstract: A method for manufacturing a monolithic ceramic electronic component includes preparing a mother block including ceramic green sheets stacked on each other, and an internal electrode pattern arranged along interfaces between the ceramic green sheets, cutting the mother block along first and second cutting lines that are perpendicular or substantially perpendicular to each other to obtain green chips each having a laminated structure including ceramic layers and internal electrodes in a raw state, the internal electrodes being exposed on a cut side surface produced by cutting along the first cutting line, forming a raw ceramic protective layer on the cut side surface to obtain a raw component body, and firing the raw component body, wherein the cut side surface is treated with a degreasing agent.
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公开(公告)号：US20170133157A1
公开(公告)日：2017-05-11
申请号：US15415986
申请日：2017-01-26
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Daiki FUKUNAGA , Hideaki TANAKA , Koji MORIYAMA
CPC classification number: H01G4/30 , H01G4/005 , H01G4/012 , H01G4/1218 , H01G4/1227 , H01G4/248
Abstract: A multilayer ceramic capacitor includes a ceramic body and external electrodes provided on opposite end surfaces of the ceramic body. The ceramic body includes an inner layer portion including a plurality of ceramic layers defining inner layers and a plurality of first and second internal electrodes each disposed at an interface of adjacent ones of the ceramic layers defining the inner layers, outer layer portions sandwiching the inner layer portion in a direction in which the layers are stacked, and side margin portions sandwiching the inner layer portion and the outer layer portions in a widthwise direction. The side margin portion includes pores that decrease in number along a direction from inside to outside of the ceramic body.
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公开(公告)号：US20230197340A1
公开(公告)日：2023-06-22
申请号：US18110396
申请日：2023-02-16
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Daiki FUKUNAGA , Hideaki TANAKA , Masahiro WAKASHIMA , Daisuke HAMADA , Hironori TSUTSUMI , Satoshi MAENO , Ryota ASO , Koji MORIYAMA , Akihiro TSURU
CPC classification number: H01G4/1227 , H01G4/012 , H01G4/0085 , H01G4/2325 , H01G4/224 , H01G4/30
Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
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Patent Agency Ranking
公开(公告)号：US20200066446A1
公开(公告)日：2020-02-27
申请号：US16547641
申请日：2019-08-22
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Daiki FUKUNAGA , Hideaki TANAKA , Masahiro WAKASHIMA , Daisuke HAMADA , Hironori TSUTSUMI , Satoshi MAENO , Ryota ASO , Koji MORIYAMA , Akihiro TSURU
Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
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公开(公告)号：US20200020483A1
公开(公告)日：2020-01-16
申请号：US16568573
申请日：2019-09-12
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideaki TANAKA , Daiki FUKUNAGA , Koji MORIYAMA
Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.
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公开(公告)号：US20190189355A1
公开(公告)日：2019-06-20
申请号：US16285286
申请日：2019-02-26
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hideaki TANAKA , Daiki FUKUNAGA , Koji MORIYAMA
Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.
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公开(公告)号：US20150340155A1
公开(公告)日：2015-11-26
申请号：US14711975
申请日：2015-05-14
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Daiki FUKUNAGA , Hideaki TANAKA , Koji MORIYAMA
CPC classification number: H01G4/30 , H01G4/005 , H01G4/012 , H01G4/1218 , H01G4/1227 , H01G4/248
Abstract: A multilayer ceramic capacitor includes a ceramic body and external electrodes provided on opposite end surfaces of the ceramic body. The ceramic body includes an inner layer portion including a plurality of ceramic layers defining inner layers and a plurality of first and second internal electrodes each disposed at an interface of adjacent ones of the ceramic layers defining the inner layers, outer layer portions sandwiching the inner layer portion in a direction in which the layers are stacked, and side margin portions sandwiching the inner layer portion and the outer layer portions in a widthwise direction. The side margin portion includes pores that decrease in number along a direction from inside to outside of the ceramic body.
Abstract translation: 多层陶瓷电容器包括陶瓷体和设置在陶瓷体的相对端面上的外部电极。 陶瓷体包括内层部分，其包括限定内层的多个陶瓷层和多个第一和第二内部电极，每个内部电极设置在限定内部层的相邻陶瓷层的界面处，外层部分夹在内层 在层叠方向上的部分，以及在宽度方向上夹着内层部分和外层部分的侧边缘部分。 侧边缘部分包括沿着从陶瓷体的内部到外部的方向减少数量的孔。
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公开(公告)号：US20240312712A1
公开(公告)日：2024-09-19
申请号：US18675491
申请日：2024-05-28
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Daiki FUKUNAGA , Hideaki TANAKA , Masahiro WAKASHIMA , Daisuke HAMADA , Hironori TSUTSUMI , Satoshi MAENO , Ryota ASO , Koji MORIYAMA , Akihiro TSURU
CPC classification number: H01G4/1227 , H01G4/0085 , H01G4/012 , H01G4/224 , H01G4/2325 , H01G4/30
Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
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