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公开(公告)号：US20250096749A1
公开(公告)日：2025-03-20
申请号：US18969967
申请日：2024-12-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Seiko NETSU , Masatoshi HASE
Abstract: A power amplifier circuit includes one or a plurality of amplification stages. A first amplification stage includes a first amplifier and a second amplifier that amplify a differential signal, a first capacitor electrically connected between an output terminal of the first amplifier and an input terminal of the second amplifier, a second capacitor electrically connected between an input terminal of the first amplifier and an output terminal of the second amplifier, a first resonant circuit and a first resistor that are electrically connected in series with each other and are electrically connected between the output terminal and the input terminal of the first amplifier, and a second resonant circuit and a second resistor that are electrically connected in series with each other and are electrically connected between the output terminal and the input terminal of the second amplifier.
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公开(公告)号：US20240388264A1
公开(公告)日：2024-11-21
申请号：US18785713
申请日：2024-07-26
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masatoshi HASE , Seiko NETSU
Abstract: A Class E amplifier is configured to amplify a differential signal. Two output nodes of the Class E amplifier are connected to the power supply terminal with at least one choke inductor interposed therebetween. The Class E amplifier includes two transistors. The two transistors each includes a base or a gate connected to a corresponding one of two input nodes of the Class E amplifier and a collector or a drain connected to a corresponding one of the two output nodes of the Class E amplifier. First capacitors are each connected between the collector or the drain and an emitter or a source of a corresponding one of the two transistors. A first inductor is connected between the collector or the drain of one of the two transistors and the collector or the drain of the other of the two transistors.
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Patent Agency Ranking
公开(公告)号：US20240146271A1
公开(公告)日：2024-05-02
申请号：US18499666
申请日：2023-11-01
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masatoshi HASE , Koudai SUGIYAMA , Masamichi TOKUDA , Seiko NETSU
CPC classification number: H03F3/60 , H01P5/10 , H01P5/18 , H03F1/56 , H03F2200/451
Abstract: A first transmission line transformer receives and outputs an unbalanced signal and performs impedance transformation. A second transmission line transformer performs unbalanced-to-balanced transformation. The first transmission line transformer includes a first main line and a first sub-line. The direction of the first main line is identical to the direction of the first sub-line. An end of the first sub-line is grounded. An end of the first main line is coupled to the unbalanced-signal input/output node. The second transmission line transformer includes a second main line and a second sub-line. The direction of the second main line is identical to a direction of the second sub-line. An end of the second main line and the second sub-line are grounded. An end of the second main line and the second sub-line are coupled to the balanced-signal input/output nodes.
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公开(公告)号：US20240333231A1
公开(公告)日：2024-10-03
申请号：US18619743
申请日：2024-03-28
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masatoshi HASE , Seiko NETSU , Shingo YANAGIHARA
CPC classification number: H03F1/3211 , H03F1/0288 , H03F3/245 , H03F3/602 , H03F2200/451
Abstract: A power amplifier circuit includes a distortion compensation amplifier circuit that includes a first amplifier that amplifies a first signal distributed from an input signal, and a second amplifier connected in parallel to the first amplifier, that amplifies a second signal distributed from the input signal and having a different phase from the first signal, and outputs an amplified signal obtained by combining a signal output from the first amplifier and the second amplifier, and an output amplifier circuit that outputs an output signal obtained by amplifying the amplified signal. The distortion compensation amplifier circuit further includes a control circuit that controls, based on power of the input signal, the first gain and the second gain to compensate for a change in a phase of the output amplifier circuit with respect to a change in the power of the signal input to the output amplifier circuit.
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公开(公告)号：US20240162871A1
公开(公告)日：2024-05-16
申请号：US18504274
申请日：2023-11-08
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masatoshi HASE , Koudai SUGIYAMA , Masamichi TOKUDA , Seiko NETSU
IPC: H03F3/45
CPC classification number: H03F3/45475 , H03F2200/06 , H03F2200/09 , H03F2200/451
Abstract: A main line (transmission line) has a first end and a second end. A sub-line (transmission line) coupled to the main line has a third end and a fourth end. The main line and the sub-line are coupled to each other. A direction of the main line is identical to a direction of the sub-line. An unbalanced node is connected to the first end. The first balanced node is connected to the first end, and the second balanced node is connected to the fourth end. The second end and the third end are connected to a reference potential. A first LC resonant circuit is connected between the first balanced node and the unbalanced node, the second balanced node and the fourth end, or the first end and the unbalanced node.
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公开(公告)号：US20240396516A1
公开(公告)日：2024-11-28
申请号：US18792234
申请日：2024-08-01
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Seiko NETSU , Masatoshi HASE
Abstract: A balanced-to-unbalanced transformer circuit is formed with a transmission line including a main line and a sub-line which are coupled to each other. The main line comprises at least one wiring line. The sub-line comprises multiple wiring lines which are connected in parallel to one another and which are other than the at least one wiring line. Each of the wiring lines of the sub-line is coupled to the at least one wiring line of the main line.
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公开(公告)号：US20240162870A1
公开(公告)日：2024-05-16
申请号：US18503549
申请日：2023-11-07
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masatoshi HASE , Koudai SUGIYAMA , Masamichi TOKUDA , Seiko NETSU
IPC: H03F3/45
CPC classification number: H03F3/45475 , H03F2200/06 , H03F2200/09 , H03F2200/451
Abstract: A main line (transmission line) having a first end and a second end. A sub-line (transmission line) coupled to the main line. An unbalanced signal is input to and output from an unbalanced node connected to the first end. A balanced signal is input to and output from a first balanced node and a second balanced node. The main line and the sub-line are coupled to each other. A direction of the main line is identical to a direction of the sub-line. The second end and the third end are connected to a reference potential. The first balanced node and the second balanced node are connected to the unbalanced node and the fourth end, respectively. A first LC resonant circuit is connected between the second end and the reference potential or the third end and the reference potential.
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