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公开(公告)号：US20110260791A1
公开(公告)日：2011-10-27
申请号：US13141719
申请日：2009-11-30
CPC分类号： H03F3/2176 , H01L2224/48091 , H01L2224/48137 , Y10T29/4902 , H01L2924/00014
摘要： A pre-driver for an amplifier comprising a load network in which the following elements are connected in the following order: a resistor-an inductor-a capacitor. Also described are a power amplifier comprising such a pre-driver, a method of fabricating a pre-driver for an amplifier, and a method of performing power amplification.
摘要翻译： 一种用于放大器的预驱动器，包括负载网络，其中以下列顺序连接以下元件：电阻器 - 电感器 - 电容器。 还描述了包括这种预驱动器的功率放大器，制造用于放大器的预驱动器的方法以及执行功率放大的方法。
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公开(公告)号：US08373508B2
公开(公告)日：2013-02-12
申请号：US13141719
申请日：2009-11-30
IPC分类号： H03F3/04
CPC分类号： H03F3/2176 , H01L2224/48091 , H01L2224/48137 , Y10T29/4902 , H01L2924/00014
摘要： A pre-driver for an amplifier comprising a load network in which the following elements are connected in the following order: a resistor-an inductor-a capacitor. Also described are a power amplifier comprising such a pre-driver, a method of fabricating a pre-driver for an amplifier, and a method of performing power amplification.
摘要翻译： 一种用于放大器的预驱动器，包括负载网络，其中以下列顺序连接以下元件：电阻器 - 电感器 - 电容器。 还描述了包括这种预驱动器的功率放大器，制造用于放大器的预驱动器的方法以及执行功率放大的方法。
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公开(公告)号：US20110273234A1
公开(公告)日：2011-11-10
申请号：US12773498
申请日：2010-05-04
IPC分类号： H03F3/68
CPC分类号： H03F3/24 , H03F1/0294 , H03F1/565 , H03F3/195 , H03F2200/204 , H03F2200/387 , H03F2200/451
摘要： Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. The power transistor circuitry, the broadband combiner, and the impedance matching filter are integrated in a unified package. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described.
摘要翻译： 各种实施例涉及用于高功率基站的可重构集成数字Chireix异相功率放大器，并描述了所述设计的相关方法。 功率放大器可以包括具有多个功率晶体管和分流串联电路（L1C1，L2C2）的功率晶体管电路，具有Chireix补偿元件的宽带组合器和阻抗匹配滤波器。 功率晶体管电路，宽带组合器和阻抗匹配滤波器集成在一个统一的封装中。 在一个实施例中，功率放大器以实际开关模式实现，以便于Chireix补偿元件的集成，以使Chireix功率放大器可调谐。 还描述了驱动Chireix功率放大器结构的方法。
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公开(公告)号：US08526536B2
公开(公告)日：2013-09-03
申请号：US13320013
申请日：2010-05-15
CPC分类号： H03F1/0294 , H03F3/72 , H03F2200/336
摘要： A transmitter (200) comprises a first Chireix compensation circuit (230, 232, 238, 240) and a second Chireix compensation circuit (234, 236, 238, 240), wherein each Chireix compensation circuit has two inputs and two outputs. Two constant envelope input signals (22, 224) to be amplified are guided by a switch (226) to either the first or second Chireix amplifier unit. The selection as such depends on the phase (212) of the input signals to be amplified. The outputs of the two Chireix compensation circuits are cross-coupled to an inductive load (242). A Chireix inductor (238) and a Chireix capacitor (240), each having one terminal grounded, are also connected to the inductive load (242). By switching the signals to be amplified in response to their phase, optimum matching is ensured.
摘要翻译： 发射机（200）包括第一Chireix补偿电路（230,232,238,240）和第二Chireix补偿电路（234,236,238,240），其中每个Chireix补偿电路具有两个输入和两个输出。 要放大的两个恒定包络线输入信号（22,224）由开关（226）引导到第一或第二Chireix放大器单元。 这样的选择取决于要放大的输入信号的相位（212）。 两个Chireix补偿电路的输出交叉耦合到感性负载（242）。 每个具有一个端子接地的Chireix电感器（238）和Chireix电容器（240）也连接到电感负载（242）。 通过根据其相位切换待放大的信号，确保最佳匹配。
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公开(公告)号：US08203386B2
公开(公告)日：2012-06-19
申请号：US12773498
申请日：2010-05-04
IPC分类号： H03F3/68
CPC分类号： H03F3/24 , H03F1/0294 , H03F1/565 , H03F3/195 , H03F2200/204 , H03F2200/387 , H03F2200/451
摘要： Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. The power transistor circuitry, the broadband combiner, and the impedance matching filter are integrated in a unified package. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described.
摘要翻译： 各种实施例涉及用于高功率基站的可重构集成数字Chireix异相功率放大器，并描述了所述设计的相关方法。 功率放大器可以包括具有多个功率晶体管和分流串联电路（L1C1，L2C2）的功率晶体管电路，具有Chireix补偿元件的宽带组合器和阻抗匹配滤波器。 功率晶体管电路，宽带组合器和阻抗匹配滤波器集成在一个统一的封装中。 在一个实施例中，功率放大器以实际开关模式实现，以便于Chireix补偿元件的集成，以使Chireix功率放大器可调谐。 还描述了驱动Chireix功率放大器结构的方法。
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公开(公告)号：US20120069930A1
公开(公告)日：2012-03-22
申请号：US13320013
申请日：2010-05-15
IPC分类号： H04L27/00
CPC分类号： H03F1/0294 , H03F3/72 , H03F2200/336
摘要： A transmitter (200) comprises a first Chireix compensation circuit (230, 232, 238, 240) and a second Chireix compensation circuit (234, 236, 238, 240), wherein each Chireix compensation circuit has two inputs and two outputs. Two constant envelope input signals (22, 224) to be amplified are guided by a switch (226) to either the first or second Chireix amplifier unit. The selection as such depends on the phase (212) of the input signals to be amplified. The outputs of the two Chireix compensation circuits are cross-coupled to an inductive load (242). A Chireix inductor (238) and a Chireix capacitor (240), each having one terminal grounded, are also connected to the inductive load (242). By switching the signals to be amplified in response to their phase, optimum matching is ensured.
摘要翻译： 发射机（200）包括第一Chireix补偿电路（230,232,238,240）和第二Chireix补偿电路（234,236,238,240），其中每个Chireix补偿电路具有两个输入和两个输出。 要放大的两个恒定包络线输入信号（22,224）由开关（226）引导到第一或第二Chireix放大器单元。 这样的选择取决于要放大的输入信号的相位（212）。 两个Chireix补偿电路的输出交叉耦合到感性负载（242）。 每个具有一个端子接地的Chireix电感器（238）和Chireix电容器（240）也连接到电感负载（242）。 通过根据其相位切换待放大的信号，确保最佳匹配。
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7.发明授权公开(公告)号：US08570101B2
公开(公告)日：2013-10-29
申请号：US13128197
申请日：2009-11-06
IPC分类号： H03F3/38
CPC分类号： H03F1/0294
摘要： Power reduction in transmitters is very important. One method to realize reduction is to make use of switching power amplifiers (PA) that have a better efficiency. Switching PA concepts are only possible in combination with suitable modulation methods like pulse width modulation (PWM) and out-phasing concepts. However, PWM and out-phasing concepts rely on accurate phase control and duty cycle of the signals. Digitally generation of signals of variable duty cycles and phase is proposed without sacrificing their accuracy. Accordingly, a out-phasing power amplifier arrangement is disclosed, where the generation of the out-phasing angle (θ) and duty cycles (d1 and d2) are controlled by a set of n-bit digital input words (D1, D2, D3, D4). The baseband phase information (φ(t)) is phase modulated back to radio frequency and used as the clock signal of digital circuitry for phase and duty cycle generation after being frequency multiplied by 2n-1. The resolution of the out-phasing angle and of the duty cycle is 2π/2n and 2π/2n-1 equivalently. The resolution of the phase information φ is dependent on the PM realization.
摘要翻译： 发射机的功率降低非常重要。 实现减少的一种方法是利用具有更好效率的开关功率放大器（PA）。 开关PA概念只能与诸如脉冲宽度调制（PWM）和分相概念的合适的调制方法相结合。 然而，PWM和输出相位概念依赖于信号的精确相位控制和占空比。 提出了可变占空比和相位的信号的数字生成，而不牺牲其精度。 因此，公开了一种分相功率放大器装置，其中产生相位角（θ）和占空比（d1和d2）由一组n位数字输入字（D1，D2，D3）控制 ，D4）。 基带相位信息（phi（t））被相位调制回射频，并且用作数字电路的时钟信号，用于在频率乘以2n-1之后产生相位和占空比。 相位角和占空比的分辨率等于2pi / 2n和2pi / 2n-1。 相位信息phi的分辨率取决于PM实现。
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公开(公告)号：US08373507B2
公开(公告)日：2013-02-12
申请号：US13142029
申请日：2009-12-11
IPC分类号： H02H7/20
CPC分类号： H03F3/2176 , H03F1/0277 , H03F1/523 , H03F3/211 , H03F3/245 , H03F3/72 , H03F2200/471 , H03F2203/21178 , H03F2203/7236
摘要： A power amplifier, for example a class-E switching power amplifier, and corresponding method, comprising: a plurality of power transistors (16), for example twelve power transistors, providing a partitioned power transistor; and a voltage sensing module (22), comprising for example voltage dividers and inverters, digitally sensing the drain voltage (2) of the partitioned power transistor to control the number of power transistors of the plurality of power transistors (16) that are switched on or off thereby controlling the drain voltage (2) which is varying for example due to antenna mismatch. The power amplifier may further comprise a memory (24) coupled to the voltage sensing module (22) for storing a history of the drain voltage (2), e.g. a history of antenna mismatch.
摘要翻译： 功率放大器，例如E类开关功率放大器，以及相应的方法，包括：多个功率晶体管（16），例如十二个功率晶体管，提供分配的功率晶体管; 以及电压感测模块（22），其包括例如分压器和反相器，数字地感测分隔的功率晶体管的漏极电压（2）以控制接通的多个功率晶体管（16）的功率晶体管的数量 或关断，从而控制例如由于天线失配而变化的漏极电压（2）。 功率放大器还可以包括耦合到电压感测模块（22）的存储器（24），用于存储漏极电压（2）的历史，例如， 天线不匹配的历史。
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公开(公告)号：US20110254630A1
公开(公告)日：2011-10-20
申请号：US13142029
申请日：2009-12-11
IPC分类号： H03F3/16
CPC分类号： H03F3/2176 , H03F1/0277 , H03F1/523 , H03F3/211 , H03F3/245 , H03F3/72 , H03F2200/471 , H03F2203/21178 , H03F2203/7236
摘要： A power amplifier, for example a class-E switching power amplifier, and corresponding method, comprising: a plurality of power transistors (16), for example twelve power transistors, providing a partitioned power transistor; and a voltage sensing module (22), comprising for example voltage dividers and inverters, digitally sensing the drain voltage (2) of the partitioned power transistor to control the number of power transistors of the plurality of power transistors (16) that are switched on or off thereby controlling the drain voltage (2) which is varying for example due to antenna mismatch. The power amplifier may further comprise a memory (24) coupled to the voltage sensing module (22) for storing a history of the drain voltage (2), e.g. a history of antenna mismatch.
摘要翻译： 功率放大器，例如E类开关功率放大器，以及相应的方法，包括：多个功率晶体管（16），例如十二个功率晶体管，提供分配的功率晶体管; 以及电压感测模块（22），其包括例如分压器和反相器，数字地感测分隔的功率晶体管的漏极电压（2）以控制接通的多个功率晶体管（16）的功率晶体管的数量 或关断，从而控制例如由于天线失配而变化的漏极电压（2）。 功率放大器还可以包括耦合到电压感测模块（22）的存储器（24），用于存储漏极电压（2）的历史，例如， 天线不匹配的历史。
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10.发明申请VARIABLE DUTY CYCLE GENERATION FOR OUT-PHASING AND PWM POWER AMPLIFIERS 失效用于外置PWM和PWM功率放大器的可变负载周期生成公开(公告)号：US20110216818A1
公开(公告)日：2011-09-08
申请号：US13128197
申请日：2009-11-06
CPC分类号： H03F1/0294
摘要： Power reduction in transmitters is very important. One method to realize reduction is to make use of switching power amplifiers (PA) that have a better efficiency. Switching PA concepts are only possible in combination with suitable modulation methods like pulse width modulation (PWM) and out-phasing concepts. However, PWM and out-phasing concepts rely on accurate phase control and duty cycle of the signals. Digitally generation of signals of variable duty cycles and phase is proposed without sacrificing their accuracy. Accordingly, a out-phasing power amplifier arrangement is disclosed, where the generation of the out-phasing angle (θ) and duty cycles (d1 and d2) are controlled by a set of n-bit digital input words (D1, D2, D3, D4). The baseband phase information (φ(t)) is phase modulated back to radio frequency and used as the clock signal of digital circuitry for phase and duty cycle generation after being frequency multiplied by 2n−1. The resolution of the out-phasing angle and of the duty cycle is 2π/2n and 2π/2n−1 equivalently. The resolution of the phase information φ is dependent on the PM realization.
摘要翻译： 发射机的功率降低非常重要。 实现减少的一种方法是利用具有更好效率的开关功率放大器（PA）。 开关PA概念只能与诸如脉冲宽度调制（PWM）和分相概念的合适的调制方法相结合。 然而，PWM和输出相位概念依赖于信号的精确相位控制和占空比。 提出了可变占空比和相位的信号的数字生成，而不牺牲其精度。 因此，公开了一种分相功率放大器装置，其中产生相位角（＆amp; t）和占空比（d1和d2）由一组n位数字输入字（D1，D2， D3，D4）。 基带相位信息（＆phgr;（t））被相位调制回射频，并且用作数字电路的时钟信号，用于在频率乘以2n-1之后产生相位和占空比。 相位角和占空比的分辨率等于2＆pgr; / 2n和2＆pgr / 2n-1。 相位信息的解析 取决于PM的实现。
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