公开(公告)号：US20230237322A1

公开(公告)日：2023-07-27

申请号：US17918945

申请日：2020-04-28

Applicant: NEC Corporation

Inventor： Seiya SHIBATA

IPC: G06N3/08 ,  G06N3/0464

CPC classification number: G06N3/08 ,  G06N3/0464

Abstract: A generation unit generates a new j-th weight matrix to be used in the convolution computation of data consisting of {(j−1)×N/g+1} to (j×N/g) channels (j=1 to g) divided after the divided number is changed over j=1 to j=g respectively. The generation unit generates the new j-th weight matrix by placing {(j−1)×G/g+1} to (j×G/g) weight matrices from the upper left to the lower right of the new j-th weight matrix in the order of {(j−1)>G/g+1} to (j×G/g) weight matrices on the diagonal line, and setting values of all components except for components at locations where the weight matrices are placed to 0.

公开(公告)号：US20230004810A1

公开(公告)日：2023-01-05

申请号：US17781539

申请日：2019-12-06

Applicant: NEC Corporation

Inventor： Seiya SHIBATA

IPC: G06N3/08

Abstract: A parameter optimization device 800 optimizes input CNN structure information and outputs optimized CNN structure information, and includes stride and dilation use layer detection means 811 for extracting stride and dilation parameter information for each convolution layer from the input CNN structure information, and stride and dilation use position modification means 812 for changing the stride and dilation parameter information of the convolution layer.

公开(公告)号：US20220171650A1

公开(公告)日：2022-06-02

申请号：US17674172

申请日：2022-02-17

Applicant: NEC Corporation

Inventor： Hideo HASEGAWA ,  Shintaro NAKANO ,  Satoru ISHII ,  Seiya SHIBATA

IPC: G06F9/455 ,  G06F9/50 ,  G06F9/48 ,  H04L41/22 ,  H04L67/10

Abstract: A management apparatus (10) includes: a storage (103) that stores information indicating a correspondence between at least one virtual network function (VNF) operating on a server and a programmable logic circuit (FPGA) capable of operating at least part of a virtual network function; and a controller (106) that causes first and second servers to perform migration of a virtual network function operating on a programmable logic circuit of the first server to the second server, on the basis of the correspondence information.

公开(公告)号：US20250103865A1

公开(公告)日：2025-03-27

申请号：US18728124

申请日：2022-01-19

Applicant: NEC Corporation

Inventor： Seiya SHIBATA

IPC: G06N3/0464

Abstract: The convolution layer conversion apparatus includes: a convolution layer detection part that detects a convolution layer containing a large kernel of a predetermined kernel size or larger in a neural network model structure provided as an input; and a convolution layer decomposition part that converts the convolution layer into a convolution layer containing a combination of a plurality of small kernels obtained by decomposing the detected large kernel into a plurality of small kernels whose kernel sizes is smaller than the predetermined size and an aggregate convolution layer that aggregates results from the convolution layer containing the combination of the plurality of small kernels, and outputs a neural network model structure in which the convolution layer is converted.

公开(公告)号：US20220172032A1

公开(公告)日：2022-06-02

申请号：US17437947

申请日：2019-03-25

Applicant: NEC Corporation

Inventor： Seiya SHIBATA ,  Yuka HAYASHI

IPC: G06N3/063

Abstract: A neural network circuit 201 is a neural network circuit divides convolution operation into convolution operation in a spatial direction and convolution operation in a channel direction, performs the respective convolution operation separately, and includes a 1×1 convolution operation circuit 10 that performs convolution in the channel direction, an SRAM 20 in which a computation result of the 1×1 convolution operation circuit 10 is stored, and an N×N convolution operation circuit 30 that performs convolution in the spatial direction for the computation result stored in the SRAM 20.

公开(公告)号：US20210110236A1

公开(公告)日：2021-04-15

申请号：US16977349

申请日：2019-02-28

Applicant: NEC CORPORATION

Inventor： Seiya SHIBATA

IPC: G06N3/04

Abstract: An inferential device, including a quantization part that quantizes a result of a convolutional operation in a convolutional neural network using input data and weights; a convolutional operation part that performs a convolutional operation using the quantized operation result as input data; and an input data conversion part that converts the input data to a first layer to enable the convolutional operation part to process both the input data to the first layer and the input data that is quantized by the quantization part in a same way.

公开(公告)号：US20240320948A1

公开(公告)日：2024-09-26

申请号：US18599715

申请日：2024-03-08

Applicant: NEC Corporation

Inventor： Seiya SHIBATA

IPC: G06V10/25 ,  G06V10/22

CPC classification number: G06V10/25 ,  G06V10/23 ,  G06V2201/07 ,  G06V2201/10

Abstract: An object detection system that can achieve both low delay and object detection accuracy is provided. A first detection unit identifies labels of objects reflected in a input frame and locations of bounding boxes of the objects. A history information generation unit assigns the same ID to the bounding boxes that share the same object, and generates history information that is information indicating a history of combination of a frame number and a location of a bounding box for each ID. A prediction unit predicts regions of the bounding boxes in latest frame, based on the history information, according to a delay that is a time required for the first detection unit to identify the labels and the locations of the bounding boxes in the input frame.

公开(公告)号：US20210201120A1

公开(公告)日：2021-07-01

申请号：US16757543

申请日：2018-10-22

Applicant: NEC Corporation

Inventor： Seiya SHIBATA

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/08 ,  G06N3/04 ,  G06K9/62

Abstract: An inference apparatus comprises a plurality of PEs (Processing Elements) and a control part. The control part operates a convolution operation in a convolutional neural network using each of a plurality of pieces of input data and a weight group including a plurality of weights corresponding to each of the plurality of pieces of input data by controlling the plurality of PEs. Further, each of the plurality of PEs executes a computation including multiplication of a single piece of the input data by a single weight and also executes multiplication included in the convolution operation using an element with a non-zero value included in each of the plurality of pieces of input data.

公开(公告)号：US20190034570A1

公开(公告)日：2019-01-31

申请号：US16070328

申请日：2017-01-31

Applicant: NEC CORPORATION

Inventor： Seiya SHIBATA ,  Takashi TAKENAKA

IPC: G06F17/50

Abstract: Provided is for reducing access latency. A high-level synthesis device includes feature quantity obtaining unit and implementation determination unit. Feature quantity obtaining unit obtains an access feature quantity including a feature quantity relating to communication between a plurality of modules by analyzing an access pattern in communication between the plurality of modules. Implementation determination unit determines an implementation method for communicating between the plurality of modules based on the obtained access feature quantity.

公开(公告)号：US20160301941A1

公开(公告)日：2016-10-13

申请号：US14772287

申请日：2014-07-25

Applicant: NEC CORPORATION

Inventor： Keiichi CHONO ,  Seiya SHIBATA ,  Takayuki ISHIDA ,  Kensuke SHIMOFURE

IPC: H04N19/40 ,  H04N19/146

CPC classification number: H04N19/40 ,  H04N19/103 ,  H04N19/146 ,  H04N19/157 ,  H04N19/176 ,  H04N19/194

Abstract: A video encoding device includes: a first video encoding section 11 for encoding an input image to generate first coded data; a buffer 12 for storing the input image; a coded data transcoding/merging section 13 for transcoding and then merging the first coded data generated by the first video encoding section 11, to generate second coded data; and a second video encoding section 14 for estimating a syntax value for encoding the input image stored in the buffer 12 based on the second coded data supplied from the coded data transcoding/merging section 13, to generate a bitstream. The first video encoding section 11 has a function of handling a first encoding process included in a second encoding process handled by the second video encoding section 14. The coded data transcoding/merging section 13 transcodes coded data by the first encoding process to coded data corresponding to the second encoding process.

Abstract translation: 视频编码装置包括：第一图像编码部分11，用于对输入图像进行编码以产生第一编码数据; 用于存储输入图像的缓冲器12; 编码数据代码转换/合并部分13，用于对由第一视频编码部分11产生的第一编码数据进行代码转换，然后合并，以产生第二编码数据; 以及第二视频编码部分14，用于基于从编码数据代码转换/合并部分13提供的第二编码数据估计用于对存储在缓冲器12中的输入图像进行编码的语法值，以生成比特流。 第一视频编码部分11具有处理包括在由第二视频编码部分14处理的第二编码处理中的第一编码处理的功能。编码数据代码转换/合并部分13通过第一编码处理将编码数据转码成对应于编码数据 到第二编码过程。