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公开(公告)号:US20160260200A1
公开(公告)日:2016-09-08
申请号:US14426860
申请日:2013-09-10
Applicant: NEC CORPORATION
Inventor: Eita KOBAYASHI , Takashi TAKENAKA
CPC classification number: G06T5/002 , G06T5/10 , G06T2207/20016 , G06T2207/20064 , H04N1/409
Abstract: Provided is an image processing device for performing noise removal in which a plurality of noise removal actions are combined while minimizing necessary resources. The image processing device is provided with: a first frequency separation unit for separating the input image by frequency into a first low-frequency component and a first high-frequency component containing a higher-frequency component than the first low-frequency component; a second frequency separation unit for separating the first low-frequency component into a second low-frequency component and a second high-frequency component containing a higher-frequency component than the second low-frequency component; a first image transform unit for performing noise removal on the second low-frequency component and the second high-frequency component and outputting the noise-removed image as a first transformed image; and a second image transform unit for performing noise removal on the first high-frequency component and the first transformed image with less resources being allocated than those allocated to the first image transform unit, and outputting the noise-removed image as a second transformed image.
Abstract translation: 提供了一种用于执行噪声去除的图像处理装置,其中组合多个噪声去除动作同时最小化必要的资源。 图像处理装置具有:第一频率分离单元,用于将输入图像按频率分离成第一低频分量和包含比第一低频分量更高频分量的第一高频分量; 用于将第一低频分量分离为第二低频分量的第二频率分离单元和包含比第二低频分量更高频分量的第二高频分量; 第一图像变换单元,用于对所述第二低频分量和所述第二高频分量执行噪声去除并输出所述噪声去除图像作为第一变换图像; 以及第二图像变换单元,用于以比分配给第一图像变换单元的资源少的资源分配对第一高频分量和第一变换图像执行噪声去除,并输出噪声去除图像作为第二变换图像。
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公开(公告)号:US20220207339A1
公开(公告)日:2022-06-30
申请号:US17607473
申请日:2019-05-08
Applicant: NEC Corporation
Inventor: Takashi TAKENAKA , Fumiyo TAKANO , Seiya SHIBATA , Hiroaki INOUE
IPC: G06N3/063
Abstract: The determining unit 72 divides channels in the 0th layer and channels in the first layer into groups whose number is equal to the number of chips that are included in an operation device executing an operation of the neural network using a learning result of the weight for each edge, respectively. The determining unit 72 determines association of the groups of the channels in the 0th layer and the groups of the channels in the first layer and the chips included in the operation device, and edges to be removed, and removes the edges to be removed. The weight assignment unit 73 stores the weights of the edges in the weight storage unit in the chip corresponding to the edge.
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公开(公告)号:US20190109765A1
公开(公告)日:2019-04-11
申请号:US16089145
申请日:2017-03-27
Applicant: NEC CORPORATION
Inventor: Seiya SHIBATA , Takashi TAKENAKA , Hideo HASEGAWA , Satoru ISHII , Shintaro NAKANO
Abstract: A network system includes multiple processing units (21-1, 21-2, 22-1, 22-2) on each of which a desired virtual network function can be configured and a management apparatus that determines a communication path that connects the processing units so as to deploy a set of desired virtual network functions. At least one of the processing units includes a first communication interface that is connectable to any different processing unit and at least one second communication interface that is directly connectable to a predetermined different processing unit. The management apparatus determines the communication path for deploying the set of the desire virtual network functions, in accordance with respective connectable communication interfaces of the processing units.
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公开(公告)号:US20220215237A1
公开(公告)日:2022-07-07
申请号:US17607540
申请日:2019-05-08
Applicant: NEC corporation
Inventor: Takashi TAKENAKA , Fumiyo TAKANO , Seiya SHIBATA , Hiroaki INOUE
Abstract: Each chip 70 includes weight storage unit for storing weights for each edge determined by learning under the condition that channels in a first layer that is a layer in a neural network and channels in a 0th layer that is a previous layer to the first layer are divided into groups whose number is equal to the number of the chips, respectively, the groups of the channels in the first layer and the groups of the channels in the 0th layer and the chips are associated, an edge is set between the channels belonging to corresponding groups, an edge is set between the channels belonging to non-corresponding groups under a restriction. The weight storage unit stores the weights determined for the edge between the channels, each of which corresponds to each chip including the weight storage unit, belonging to corresponding groups.
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公开(公告)号:US20220413806A1
公开(公告)日:2022-12-29
申请号:US17771143
申请日:2019-10-31
Applicant: NEC Corporation
Inventor: Takashi TAKENAKA , Hiroaki INOUE
Abstract: The information processing circuit 10 performs operations on layers in deep learning, and includes a product sum circuit 11 which performs a product-sum operation using input data and parameter values, and a parameter value output circuit 12 which outputs the parameter values, wherein the parameter value output circuit 12 is composed of a combinational circuit.
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公开(公告)号:US20190034570A1
公开(公告)日:2019-01-31
申请号:US16070328
申请日:2017-01-31
Applicant: NEC CORPORATION
Inventor: Seiya SHIBATA , Takashi TAKENAKA
IPC: G06F17/50
Abstract: Provided is for reducing access latency. A high-level synthesis device includes feature quantity obtaining unit and implementation determination unit. Feature quantity obtaining unit obtains an access feature quantity including a feature quantity relating to communication between a plurality of modules by analyzing an access pattern in communication between the plurality of modules. Implementation determination unit determines an implementation method for communicating between the plurality of modules based on the obtained access feature quantity.
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公开(公告)号:US20170262044A1
公开(公告)日:2017-09-14
申请号:US15508989
申请日:2015-09-07
Applicant: NEC Corporation
Inventor: Takashi TAKENAKA , Shuichi TAHARA , Kenichi OYAMA , Nobuharu KAMI , Hiroto SUGAHARA , Noboru SAKIMURA , Kosuke NISHIHARA , Naoki KASAI
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/32 , G08C17/00 , H04Q9/00 , H04W52/0219 , H04W52/0229 , Y02D70/00 , Y02D70/142 , Y02D70/162
Abstract: An information processing apparatus according to the present invention includes: a detection unit that detects detection information that is information indicating an external state of the apparatus; a communication unit that receives reception information that is a determination result given by another apparatus; and a control unit that calculates a first determination result that is a result acquired by determining a state of a surrounding of the apparatus based on the detection information and the reception information, transmits the first determination result to the another apparatus via the communication unit, and activates a necessary function for the detection unit or the communication unit and stops an unnecessary function thereof.
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