公开(公告)号：US20210399195A1

公开(公告)日：2021-12-23

申请号：US17342811

申请日：2021-06-09

Applicant: NEC Corporation

Inventor： Katsumi KIKUCHI ,  Akira MIYATA ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Kenji NANBA ,  Ayami YAMAGUCHI

IPC: H01L39/04

Abstract: A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device 1 includes a quantum chip 10 and an interposer 20 on which the quantum chip 10 is located. The interposer 20 includes an interposer substrate 22 and an interposer wiring layer 30. The interposer wiring layer 30 is disposed on a surface 22a of the interposer substrate 22 on a side on which the quantum chip 10 is located. The interposer wiring layer 30 includes, in at least a part thereof, a superconducting material layer 32 formed of a superconducting material and a non-superconducting material layer 34 formed of a non-superconducting material.

公开(公告)号：US20210399193A1

公开(公告)日：2021-12-23

申请号：US17349180

申请日：2021-06-16

Applicant: NEC Corporation

Inventor： Kenji NANBA ,  Ayami YAMAGUCHI ,  Akira MIYATA ,  Katsumi KIKUCHI ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU

IPC: H01L39/04 ,  H01L39/24

Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); and a second connection part (140) that is provided on a main surface of the interposer (112) where the first connection part (130) is arranged and is connected to a cooling plate (115).

公开(公告)号：US20210399196A1

公开(公告)日：2021-12-23

申请号：US17347784

申请日：2021-06-15

Applicant: NEC Corporation

Inventor： Katsumi KIKUCHI ,  Akira MIYATA ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Kenji NANBA ,  Ayami YAMAGUCHI

IPC: H01L39/04 ,  H01R12/71

Abstract: A quantum device capable of securing terminals for external connection is provided. A quantum device according to an example embodiment includes a quantum chip 10, an interposer 20 on which the quantum chip 10 is mounted, and a socket 40 disposed so as to be opposed to the interposer 20, the socket 40 comprising a movable pin 47 and a housing 45 supporting the movable pin 47, in which at least one end of the movable pin 47, which includes the one end and the other end opposite to the one end, is movable relative to the housing 45, the one end being in electrical contact with a terminal of the interposer 20, and the other end is in an electrical contact with a terminal of a board 50 on which a connector 51 is formed, the connector 51 being configured to serve as an external input/output.

公开(公告)号：US20210398893A1

公开(公告)日：2021-12-23

申请号：US17345426

申请日：2021-06-11

Applicant: NEC Corporation

Inventor： Katsumi KIKUCHI ,  Akira MIYATA ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Kenji NANBA ,  Ayami YAMAGUCHI

IPC: H01L23/498 ,  H01L39/02

Abstract: A quantum device capable of improving a cooling effect while securing the number of terminals is provided. A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, and a metal film 70 disposed in a part of the interposer 20 that is in contact with a sample stage 30 having a cooling function, and a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22.

公开(公告)号：US20230276717A1

公开(公告)日：2023-08-31

申请号：US18007765

申请日：2020-06-05

Applicant: NEC Corporation

Inventor： Akira MIYATA ,  Katsumi KIKUCHI ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Tomohiro YAMAJI ,  Tsuyoshi YAMAMOTO ,  Yoshihito HASHIMOTO

IPC: H10N60/10 ,  G06N10/40

CPC classification number: H10N60/10 ,  G06N10/40

Abstract: Provided are an oscillator and a quantum computer capable of suppressing an occupied area of a circuit. An oscillator (300) includes a resonator (100) including a plurality of loop circuits in which a first superconducting line (112a), a first Josephson junction (111a), a second superconducting line (112b), and a second Josephson junction (111b) are annularly connected, and a magnetic field application circuit (200) including an electrode that goes around in a predetermined shape and configured to apply a magnetic field to the loop circuit, in which the electrode is arranged so as to face at least two of the loop circuits.

公开(公告)号：US20210408354A1

公开(公告)日：2021-12-30

申请号：US17357094

申请日：2021-06-24

Applicant: NEC Corporation

Inventor： Katsumi KIKUCHI ,  Akira MIYATA ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Kenji NANBA ,  Ayami YAMAGUCHI

IPC: H01L39/04

Abstract: To provide a quantum device capable of preventing a connection member connecting a quantum chip with an interposer from being broken. The quantum device 1 includes at least one quantum chip 10, at least one interposer 20 on which the at least one quantum chip 10 is mounted, and a plurality of connection members 30 formed of a conductor. The plurality of connection members 30 are disposed between the quantum chip 10 and the interposer 20, and connect the quantum chip 10 with the interposer 20. The size of the connection member 30 on the surface along the mounting surface 20s of the interposer 20 is changed according to the position thereof relative to the quantum chip 10.

公开(公告)号：US20210399197A1

公开(公告)日：2021-12-23

申请号：US17347820

申请日：2021-06-15

Applicant: NEC Corporation

Inventor： Katsumi KIKUCHI ,  Akira MIYATA ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Kenji NANBA ,  Ayami YAMAGUCHI

IPC: H01L39/22 ,  H01L39/02 ,  G06N10/00 ,  H01L27/18

Abstract: A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.

公开(公告)号：US20210399194A1

公开(公告)日：2021-12-23

申请号：US17349281

申请日：2021-06-16

Applicant: NEC Corporation

Inventor： Kenji NANBA ,  Ayami YAMAGUCHI ,  Akira MIYATA ,  Katsumi KIKUCHI ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU

IPC: H01L39/04 ,  H01L39/24

Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); and a connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111), in which the connection part (130) includes: a plurality of pillars (131) arranged on a main surface of the interposer (112); and a metal film (132) provided on a surface of the plurality of pillars (131) in such a way that it contacts the wiring layer of the quantum chip (111) and the thickness of the metal film at outer peripheral parts of the tip of each of the plurality of pillars (131) becomes larger than the thickness of the metal film at a center part of the tip of each of the plurality of pillars (131).

公开(公告)号：US20180269541A1

公开(公告)日：2018-09-20

申请号：US15542511

申请日：2016-01-15

Applicant: NEC Corporation

Inventor： Kenji KOBAYASHI ,  Masato YANO ,  Suguru WATANABE ,  Hisato SAKUMA ,  Koji KUDO

IPC: H01M10/44 ,  H01M10/42 ,  H01M10/0525 ,  H02J7/00

CPC classification number: H01M10/441 ,  H01M10/0525 ,  H01M10/425 ,  H01M10/482 ,  H01M2010/4278 ,  H01M2220/20 ,  H02J3/32 ,  H02J7/0021 ,  H02J7/0047 ,  H02J7/007 ,  H02J2007/005

Abstract: A storage cell control system configured to perform charge/discharge control for a plurality of storage cells under control based on a power adjustment request from a power system includes: a power storage capacity calculating means configured to calculate a current power storage capacity of the storage cell based on storage cell information of the storage cell; a target power storage capacity setting means configured to set a target power storage capacity in stopping an operation of the storage cell; a capacity degradation speed calculating means configured to calculate a current capacity degradation speed and a target capacity degradation speed with respect to each power storage capacity by applying the current power storage capacity and the target power storage capacity to capacity degradation speed correlation information set in advance; and a power distributing means configured to distribute power to the plurality of storage cells in such a manner that when it is assumed that t is an elapsed time from start of operation, a capacity degradation amount DSOCvaried(t) is a time integral value of a capacity degradation speed in a case where the capacity degradation speed varies according to a power storage capacity, and a capacity degradation amount DSOCfixed(t) is a time integral value of a capacity degradation speed in a case where the capacity degradation speed is fixed regardless of a power storage capacity, a capacity degradation amount minimization condition: a capacity degradation amount DSOCvaried(t)≤a capacity degradation amount DSOCfixed(t) is satisfied.

公开(公告)号：US20240234293A9

公开(公告)日：2024-07-11

申请号：US18226866

申请日：2023-07-27

Applicant: NEC Corporation

Inventor： Katsumi KIKUCHI ,  Akira MIYATA ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Kenji NANBA ,  Ayami YAMAGUCHI

IPC: H01L23/498 ,  G06N10/40 ,  H01L23/13 ,  H01L23/367 ,  H10N60/81 ,  H10N69/00

CPC classification number: H01L23/49888 ,  G06N10/40 ,  H01L23/13 ,  H01L23/3677 ,  H10N60/815 ,  H10N69/00 ,  H01L23/36

Abstract: A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device includes a quantum chip and an interposer on which the quantum chip is located. The interposer includes an interposer substrate and an interposer wiring layer. The interposer wiring layer is disposed on a surface of the interposer substrate on a side on which the quantum chip is located. The interposer wiring layer includes, in at least a part thereof, a superconducting material layer formed of a superconducting material and a non-superconducting material layer formed of a non-superconducting material.