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    DIFFERENTIAL DIFFERENCE AMPLIFIER CIRCUIT HAVING VARIABLE TRANSCONDUCTANCE
    1.
    发明申请
    DIFFERENTIAL DIFFERENCE AMPLIFIER CIRCUIT HAVING VARIABLE TRANSCONDUCTANCE 审中-公开

    公开(公告)号：US20190385536A1

    公开(公告)日：2019-12-19

    申请号：US16009290

    申请日：2018-06-15

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Chih-Hsien CHOU ,  Po-Yu TSENG ,  Jhih-Siou CHENG

    IPC: G09G3/3283 ,  H03F3/45 ,  G09G3/36

    Abstract: The differential difference amplifier circuit includes a differential input stage circuit, a loading stage circuit coupled to the differential input stage circuit, and an output stage circuit coupled to the loading stage circuit. The output stage circuit is configured to generate an output signal. The differential input stage circuit includes a first differential pair having a first transconductance and a second differential pair having a second transconductance. The first differential pair is biased by a first current source and receives a first input signal and the output signal. The second differential pair is biased by a second current source and receives a second input signal and the output signal. At least one of the first transconductance and the second transconductance is adjusted according to the image data.

    VIDEO TRANSMISSION SYSTEM
    3.
    发明申请
    VIDEO TRANSMISSION SYSTEM 审中-公开

    公开(公告)号：US20170366759A1

    公开(公告)日：2017-12-21

    申请号：US15676956

    申请日：2017-08-14

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Jhih-Siou CHENG ,  Yi-Chuan LIU ,  Hung-Cheng HSIAO ,  Ying-Wen CHOU

    IPC: H04N5/268 ,  G06F13/40 ,  H04N5/38 ,  H04N5/44

    CPC classification number: H04N5/268 ,  G06F13/4086 ,  H04N5/38 ,  H04N5/44

    Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

    BUFFER CIRCUIT, PANEL MODULE, AND DISPLAY DRIVING METHOD
    4.
    发明申请
    BUFFER CIRCUIT, PANEL MODULE, AND DISPLAY DRIVING METHOD 有权
    缓冲电路，面板模块和显示驱动方法

    公开(公告)号：US20150228234A1

    公开(公告)日：2015-08-13

    申请号：US14339753

    申请日：2014-07-24

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Chieh-An LIN ,  Chun-Yung CHO ,  Jhih-Siou CHENG

    IPC: G09G3/36 ,  G05F3/16

    CPC classification number: G09G3/3614 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0291

    Abstract: A buffer circuit, a display module, and a display driving method are disclosed. The buffer circuit comprises a positive polarity buffer, a negative polarity buffer. The positive polarity buffer receives a first supply voltage and a second supply voltage to output a positive reference voltage to a positive resistance string. The second supply voltage is less than the first supply voltage. The negative polarity buffer receives the second supply voltage and a third supply voltage to output a negative reference voltage to a negative resistance string. The third supply voltage is less than the second supply voltage.

    Abstract translation: 公开了一种缓冲电路，显示模块和显示驱动方法。 缓冲电路包括正极性缓冲器，负极性缓冲器。 正极性缓冲器接收第一电源电压和第二电源电压，以将正参考电压输出到正电阻串。 第二电源电压小于第一电源电压。 负极性缓冲器接收第二电源电压和第三电源电压，以将负参考电压输出到负电阻串。 第三电源电压小于第二电源电压。

    BUFFER CIRCUIT, PANEL MODULE, AND DISPLAY DRIVING METHOD
    5.
    发明申请
    BUFFER CIRCUIT, PANEL MODULE, AND DISPLAY DRIVING METHOD 审中-公开

    公开(公告)号：US20180254012A1

    公开(公告)日：2018-09-06

    申请号：US15969763

    申请日：2018-05-02

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Chieh-An LIN ,  Chun-Yung CHO ,  Jhih-Siou CHENG

    IPC: G09G3/36

    CPC classification number: G09G3/3614 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0291

    Abstract: A buffer circuit, a display module, and a display driving method are disclosed. The buffer circuit comprises a first polarity buffer, a negative polarity buffer. The first polarity buffer receives a first supply voltage and a second supply voltage to output a first reference voltage to a first resistance string. The second supply voltage is less than the first supply voltage. The negative polarity buffer receives the second supply voltage and a third supply voltage to output a negative reference voltage to a negative resistance string. The third supply voltage is less than the second supply voltage.

    DRIVING CIRCUIT AND VOLTAGE MODULATION METHOD
    7.
    发明公开
    DRIVING CIRCUIT AND VOLTAGE MODULATION METHOD 审中-公开

    公开(公告)号：US20230156880A1

    公开(公告)日：2023-05-18

    申请号：US17650855

    申请日：2022-02-14

    Applicant: NOVATEK Microelectronics Corp.

    Inventor： Yi-Je SUEN ,  Po-Hsiang FANG ,  Jhih-Siou CHENG ,  Yung-Te CHANG ,  Hung-Ho HUANG

    IPC: H05B45/10 ,  H05B45/30

    CPC classification number: H05B45/10 ,  H05B45/30

    Abstract: The present disclosure provides a driving circuit, configured to couple to a light emitting diode (LED) and a power supply circuit. The driving circuit includes a comparator, a serial input interface, and an integrating unit. The comparator is configured to couple to the LED and determine whether a cathode voltage of the LED is lower than a threshold value and generate a monitoring data. The serial input interface is configured to receive a serial input data from a previous driving circuit. The integrating unit is coupled to the comparator and the serial input interface and configured to integrate the monitoring data and the serial input data to generate an output data. The output data is transmitted to a following driving circuit or feedbacked to the power supply circuit in order to modulate a power voltage that the power circuit provides to the LED.

    DIFFERENTIAL DIFFERENCE AMPLIFIER CIRCUIT HAVING VARIABLE TRANSCONDUCTANCE
    8.
    发明申请
    DIFFERENTIAL DIFFERENCE AMPLIFIER CIRCUIT HAVING VARIABLE TRANSCONDUCTANCE 审中-公开

    公开(公告)号：US20200211472A1

    公开(公告)日：2020-07-02

    申请号：US16815129

    申请日：2020-03-11

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Chih-Hsien CHOU ,  Po-Yu TSENG ,  Jhih-Siou CHENG

    IPC: G09G3/3283 ,  H03F3/45 ,  G09G3/36

    Abstract: The differential difference amplifier circuit includes a differential input stage circuit, a loading stage circuit coupled to the differential input stage circuit, and an output stage circuit coupled to the loading stage circuit. The output stage circuit is configured to generate an output signal. The differential input stage circuit includes a first differential pair having a first transconductance and a second differential pair having a second transconductance. The first differential pair is biased by a first current source and receives a first input signal and the output signal. The second differential pair is biased by a second current source and receives a second input signal and the output signal. At least one of the first transconductance and the second transconductance is adjusted according to the image data.

    VIDEO TRANSMISSION SYSTEM
    9.
    发明申请
    VIDEO TRANSMISSION SYSTEM 有权
    视频传输系统

    公开(公告)号：US20150326813A1

    公开(公告)日：2015-11-12

    申请号：US14328078

    申请日：2014-07-10

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Jhih-Siou CHENG ,  Yi-Chuan LIU ,  Hung-Cheng HSIAO ,  Ying-Wen CHOU

    IPC: H04N5/38 ,  H04N5/268 ,  H04N5/44

    CPC classification number: H04N5/268 ,  G06F13/4086 ,  H04N5/38 ,  H04N5/44

    Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

    Abstract translation: 公开了一种视频传输系统。 视频传输系统包括多点总线，第一源驱动芯片，第二源驱动芯片和定时控制器。 第一源极驱动芯片包括第一源极驱动电路和第一端子电路。 第一终端电路耦合到多点总线和第一源极驱动电路，用于提供第一端子电阻器。 第二源极驱动芯片包括第二源极驱动电路和第二端子电路。 第二端子电路耦合到多点总线和第二源极驱动电路，用于提供第二端子电阻器。 定时控制器通过多点总线耦合到第一源驱动芯片和第二源驱动芯片。

    INTEGRATED CIRCUIT AND TEST SYSTEM THEREOF
    10.
    发明申请
    INTEGRATED CIRCUIT AND TEST SYSTEM THEREOF 审中-公开
    集成电路及其测试系统

    公开(公告)号：US20140026009A1

    公开(公告)日：2014-01-23

    申请号：US13843186

    申请日：2013-03-15

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Jhih-Siou CHENG ,  Pang-Chan Hung

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/3172

    Abstract: An integrated circuit includes an input unit, a core processor and M output buffers, where M is a natural number greater than 1. The input unit has an output control pin, and receives an output control signal. The core processor is coupled to the input unit, and receives the output control signal to provide M output control signals. The M output buffers are coupled to the core processor, and are time-division multiplexing and enabled in response to the M output control signals, respectively, to output M output signals in M operation periods, respectively.

    Abstract translation: 集成电路包括输入单元，核心处理器和M个输出缓冲器，其中M是大于1的自然数。输入单元具有输出控制引脚并接收输出控制信号。 核心处理器耦合到输入单元，并接收输出控制信号以提供M个输出控制信号。 M个输出缓冲器被耦合到核心处理器，并且分别是时分复用和响应于M个输出控制信号使其能够分别在M个操作周期中输出M个输出信号。

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