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    MANAGING DEFERRED CONTEXTS IN A CACHE TILING ARCHITECTURE
    1.
    发明申请
    MANAGING DEFERRED CONTEXTS IN A CACHE TILING ARCHITECTURE 审中-公开
    在高速缓存架构中管理预留的内容

    公开(公告)号：US20140118363A1

    公开(公告)日：2014-05-01

    申请号：US14043411

    申请日：2013-10-01

    Applicant: NVIDIA Corporation

    Inventor： Ziyad S. HAKURA ,  Jeffrey A. BOLZ ,  Amanpreet GREWAL ,  Matthew JOHNSON ,  Andrei KHODAKOVSKY

    IPC: G06T1/20

    CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

    Abstract: A method for managing bind-render-target commands in a tile-based architecture. The method includes receiving a requested set of bound render targets and a draw command. The method also includes, upon receiving the draw command, determining whether a current set of bound render targets includes each of the render targets identified in the requested set. The method further includes, if the current set does not include each render target identified in the requested set, then issuing a flush-tiling-unit-command to a parallel processing subsystem, modifying the current set to include each render target identified in the requested set, and issuing bind-render-target commands identifying the requested set to the tile-based architecture for processing. The method further includes, if the current set of render targets includes each render target identified in the requested set, then not issuing the flush-tiling-unit-command.

    Abstract translation: 一种在基于瓦片的架构中管理绑定渲染目标命令的方法。 该方法包括接收所请求的一组绑定的渲染目标和绘制命令。 该方法还包括在接收到绘制命令时，确定当前的一组绑定的渲染目标是否包括在所请求的集合中识别的每个渲染目标。 该方法还包括：如果当前集合不包括在所请求的集合中识别的每个呈现目标，则向并行处理子系统发出冲洗平铺单元命令，将当前集合修改为包括在所请求的集合中标识的每个呈现目标 设置并发布将标识所请求的集合的bind-render-target命令发布到基于瓦片的架构以进行处理。 该方法还包括，如果当前呈现目标集合包括在所请求的集合中识别的每个呈现目标，则不发出flush-tiling-unit-command。

    BINDING CONSTANTS AT RUNTIME FOR IMPROVED RESOURCE UTILIZATION
    2.
    发明申请
    BINDING CONSTANTS AT RUNTIME FOR IMPROVED RESOURCE UTILIZATION 审中-公开

    公开(公告)号：US20190146817A1

    公开(公告)日：2019-05-16

    申请号：US15897090

    申请日：2018-02-14

    Applicant: NVIDIA CORPORATION

    Inventor： Ajay TIRUMALA ,  Jack CHOQUETTE ,  Manan PATEL ,  Shirish GADRE ,  Praveen KAUSHIK ,  Amanpreet GREWAL ,  Shekhar DIVEKAR ,  Andrei KHODAKOVSKY

    IPC: G06F9/455 ,  G06F8/41 ,  G06F9/38

    Abstract: A just-in-time (JIT) compiler binds constants to specific memory locations at runtime. The JIT compiler parses program code derived from a multithreaded application and identifies an instruction that references a uniform constant. The JIT compiler then determines a chain of pointers that originates within a root table specified in the multithreaded application and terminates at the uniform constant. The JIT compiler generates additional instructions for traversing the chain of pointers and inserts these instructions into the program code. A parallel processor executes this compiled code and, in doing so, causes a thread to traverse the chain of pointers and bind the uniform constant to a uniform register at runtime. Each thread in a group of threads executing on the parallel processor may then access the uniform constant.

    MANAGING MEMORY REGIONS TO SUPPORT SPARSE MAPPINGS
    4.
    发明申请
    MANAGING MEMORY REGIONS TO SUPPORT SPARSE MAPPINGS 有权
    管理存储区域来支持SPARSE映射

    公开(公告)号：US20150097847A1

    公开(公告)日：2015-04-09

    申请号：US14046064

    申请日：2013-10-04

    Applicant: NVIDIA CORPORATION

    Inventor： Jonathan DUNAISKY ,  Henry Packard MORETON ,  Jeffrey A. BOLZ ,  Yury Y. URALSKY ,  James Leroy DEMING ,  Rui M. BASTOS ,  Patrick R. BROWN ,  Amanpreet GREWAL ,  Christian AMSINCK ,  Poornachandra RAO ,  Jerome F. DULUK, JR. ,  Andrew J. TAO

    IPC: G09G5/39 ,  G06T1/60

    CPC classification number: G09G5/39 ,  G06F12/0897 ,  G06F12/1027 ,  G06T1/60

    Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

    Abstract translation: 本发明的一个实施例包括被配置为管理稀疏映射的存储器管理单元（MMU）。 MMU根据指示稀疏状态的页表项（PTE）处理将虚拟地址转换为物理地址的请求。 如果MMU确定PTE不包括从虚拟地址到物理地址的映射，则MMU将根据稀疏状态对该请求进行响应。 如果稀疏状态为活动状态，则MMU将根据请求的类型是否为写入操作确定物理地址，然后生成请求的确认。 相比之下，如果稀疏状态不活动，则MMU会生成页面错误。 有利地，所公开的实施例使得计算机系统能够管理稀疏映射，而不会引起与页面故障和常规的基于软件的稀疏映射管理相关联的性能下降。

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