公开(公告)号：US20130293564A1

公开(公告)日：2013-11-07

申请号：US13854274

申请日：2013-04-01

Applicant: NVIDIA Corporation

Inventor： Narayan KULSHRESTHA ,  Adam Paul DREYER ,  Chad D. WALKER ,  Rui M. BASTOS

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/3004 ,  G06F9/30087

Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.

Abstract translation: 本发明的一个实施例阐述了被配置为执行彩色光栅操作和原子事务两者的CROP。 在接收到原子事务时，CROP内的分发单元向L2缓存发送读取请求以检索目的地操作数。 分配单元还将源操作数和操作代码发送到等待时间缓冲器用于存储，直到从L2高速缓存检索目的地操作数。 处理流水线将操作码，源和目的地操作数和原子标志传送到混合单元进行处理。 混合单元基于操作代码在源操作数和目标操作数上执行原子事务处理，并将原子事务的结果返回到处理流水线以存储在内部缓存中。 处理流水线将原子事务的结果写入L2高速缓存以存储在与原子事务相关联的存储单元处。

公开(公告)号：US20150097847A1

公开(公告)日：2015-04-09

申请号：US14046064

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Jonathan DUNAISKY ,  Henry Packard MORETON ,  Jeffrey A. BOLZ ,  Yury Y. URALSKY ,  James Leroy DEMING ,  Rui M. BASTOS ,  Patrick R. BROWN ,  Amanpreet GREWAL ,  Christian AMSINCK ,  Poornachandra RAO ,  Jerome F. DULUK, JR. ,  Andrew J. TAO

IPC: G09G5/39 ,  G06T1/60

CPC classification number: G09G5/39 ,  G06F12/0897 ,  G06F12/1027 ,  G06T1/60

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

Abstract translation: 本发明的一个实施例包括被配置为管理稀疏映射的存储器管理单元（MMU）。 MMU根据指示稀疏状态的页表项（PTE）处理将虚拟地址转换为物理地址的请求。 如果MMU确定PTE不包括从虚拟地址到物理地址的映射，则MMU将根据稀疏状态对该请求进行响应。 如果稀疏状态为活动状态，则MMU将根据请求的类型是否为写入操作确定物理地址，然后生成请求的确认。 相比之下，如果稀疏状态不活动，则MMU会生成页面错误。 有利地，所公开的实施例使得计算机系统能够管理稀疏映射，而不会引起与页面故障和常规的基于软件的稀疏映射管理相关联的性能下降。

公开(公告)号：US20150049110A1

公开(公告)日：2015-02-19

申请号：US13969408

申请日：2013-08-16

Applicant: NVIDIA CORPORATION

Inventor： Eric B. LUM ,  Jerome F. DULUK, JR. ,  Yury Y. URALSKY ,  Rouslan DIMITROV ,  Rui M. BASTOS

IPC: G06T11/00 ,  G06T1/60

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/503

Abstract: One embodiment sets forth a method for transforming 3-D images into 2-D rendered images using render target sample masks. A software application creates multiple render targets associated with a surface. For each render target, the software application also creates an associated render target sample mask configured to select one or more samples included in each pixel. Within the graphics pipeline, a pixel shader processes each pixel individually and outputs multiple render target-specific color values. For each render target, a ROP unit uses the associated render target sample mask to select covered samples included in the pixel. Subsequently, the ROP unit uses the render target-specific color value to update the selected samples in the render target, thereby achieving sample-level color granularity. Advantageously, by increasing the effective resolution using render target sample masks, the quality of the rendered image is improved without incurring the performance degradation associated with processing each sample individually.

Abstract translation: 一个实施例提出了一种使用渲染目标样本掩模将3-D图像变换成2-D渲染图像的方法。 软件应用程序创建与表面相关联的多个渲染目标。 对于每个渲染目标，软件应用程序还创建相关联的渲染目标样本掩模，其被配置为选择包括在每个像素中的一个或多个样本。 在图形流水线中，像素着色器单独处理每个像素，并输出多个渲染目标特定的颜色值。 对于每个渲染目标，ROP单元使用相关联的渲染目标样本掩模来选择包含在像素中的覆盖样本。 随后，ROP单元使用渲染目标特定颜色值来更新渲染目标中的所选样本，从而实现样本级颜色粒度。 有利地，通过使用渲染目标样本掩模增加有效分辨率，可以提高渲染图像的质量，而不会导致与单独处理每个样本相关联的性能下降。

公开(公告)号：US20140267366A1

公开(公告)日：2014-09-18

申请号：US14019344

申请日：2013-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jeffrey A. BOLZ ,  Mark J. KILGARD ,  Henry Packard MORETON ,  Rui M. BASTOS ,  Eric B. LUM

IPC: G06T11/00

CPC classification number: G06T15/503 ,  G06T11/203

Abstract: A graphics processing pipeline within a parallel processing unit (PPU) is configured to perform path rendering by generating a collection of graphics primitives that represent each path to be rendered. The graphics processing pipeline determines the coverage of each primitive at a number of stencil sample locations within each different pixel. Then, the graphics processing pipeline reduces the number of stencil samples down to a smaller number of color samples, for each pixel. The graphics processing pipeline is configured to modulate a given color sample associated with a given pixel based on the color values of any graphics primitives that cover the stencil samples from which the color sample was reduced. The final color of the pixel is determined by downsampling the color samples associated with the pixel.

Abstract translation: 并行处理单元（PPU）中的图形处理流水线被配置为通过生成表示要渲染的每个路径的图形基元的集合来执行路径渲染。 图形处理流水线确定每个不同像素内的多个模版样本位置上每个图元的覆盖范围。 然后，对于每个像素，图形处理管线将模板样本的数量减少到较少数量的颜色样本。 图形处理流水线被配置为基于覆盖颜色样本从其降低的模板样本的任何图形图元的颜色值来调制与给定像素相关联的给定颜色样本。 通过对与像素相关联的颜色样本进行下采样来确定像素的最终颜色。

公开(公告)号：US20140267318A1

公开(公告)日：2014-09-18

申请号：US13795693

申请日：2013-03-12

Applicant: NVIDIA CORPORATION

Inventor： Eric B. LUM ,  Justin COBB ,  Rui M. BASTOS ,  Christian ROUET

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/005

Abstract: A computer-implemented method for drawing graphical objects within a graphics processing pipeline is disclosed. The method includes determining that a bypass mode for a first primitive is a no-bypass mode. The method further includes rasterizing the first primitive to generate a first set of rasterization results. The method further includes generating a first set of colors for the first set of rasterization results via a pixel shader unit. The method further includes rasterizing a second primitive to generate a second set of rasterization results. The method further includes generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any processing operations on the second set of rasterization results. The method further includes transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further processing.

Abstract translation: 公开了一种用于在图形处理流水线内绘制图形对象的计算机实现的方法。 该方法包括确定第一原语的旁路模式是无旁路模式。 该方法还包括光栅化第一原语以产生第一组光栅化结果。 该方法还包括经由像素着色器单元为第一组光栅化结果生成第一组颜色。 该方法还包括光栅化第二原语以生成第二组光栅化结果。 该方法还包括为第二组光栅化结果生成第二组颜色，而不使像素着色器单元对第二组光栅化结果执行任何处理操作。 该方法还包括将第一组像素颜色和第二组像素颜色传输到光栅操作（ROP）单元以用于进一步处理。