公开(公告)号：US20150097847A1

公开(公告)日：2015-04-09

申请号：US14046064

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Jonathan DUNAISKY ,  Henry Packard MORETON ,  Jeffrey A. BOLZ ,  Yury Y. URALSKY ,  James Leroy DEMING ,  Rui M. BASTOS ,  Patrick R. BROWN ,  Amanpreet GREWAL ,  Christian AMSINCK ,  Poornachandra RAO ,  Jerome F. DULUK, JR. ,  Andrew J. TAO

IPC: G09G5/39 ,  G06T1/60

CPC classification number: G09G5/39 ,  G06F12/0897 ,  G06F12/1027 ,  G06T1/60

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

Abstract translation: 本发明的一个实施例包括被配置为管理稀疏映射的存储器管理单元（MMU）。 MMU根据指示稀疏状态的页表项（PTE）处理将虚拟地址转换为物理地址的请求。 如果MMU确定PTE不包括从虚拟地址到物理地址的映射，则MMU将根据稀疏状态对该请求进行响应。 如果稀疏状态为活动状态，则MMU将根据请求的类型是否为写入操作确定物理地址，然后生成请求的确认。 相比之下，如果稀疏状态不活动，则MMU会生成页面错误。 有利地，所公开的实施例使得计算机系统能够管理稀疏映射，而不会引起与页面故障和常规的基于软件的稀疏映射管理相关联的性能下降。

公开(公告)号：US20140104267A1

公开(公告)日：2014-04-17

申请号：US13651329

申请日：2012-10-12

Applicant: NVIDIA CORPORATION

Inventor： Christian AMSINCK ,  Christian ROUET ,  Tony LOUCA

IPC: G06T15/00

CPC classification number: G06T15/405 ,  G06T15/30 ,  G06T15/40 ,  G06T2200/28

Abstract: Techniques are disclosed for suppressing access to a depth processing unit associated with a graphics processing pipeline. The method includes receiving a graphics primitive from a first pipeline stage associated with the graphics processing pipeline. The method further includes determining that the graphics primitive is visible over one or more graphics primitives previously rendered to a frame buffer, and determining that the depth buffer is in a read-only mode. The method further includes suppressing an operation to transmit the graphics primitive to the depth processing unit. One advantage of the disclosed technique is that power consumption is reduced within the GPU by avoiding unnecessary accesses to the depth processing unit.

Abstract translation: 公开了用于抑制对与图形处理管道相关联的深度处理单元的访问的技术。 该方法包括从与图形处理流水线相关联的第一流水线阶段接收图形基元。 该方法还包括确定图形原语在先前呈现给帧缓冲器的一个或多个图形基元上可见，并且确定深度缓冲器处于只读模式。 该方法还包括抑制将图形基元发送到深度处理单元的操作。 所公开的技术的一个优点是通过避免对深度处理单元的不必要的访问来降低GPU内的功耗。

公开(公告)号：US20150154733A1

公开(公告)日：2015-06-04

申请号：US14097124

申请日：2013-12-04

Applicant: NVIDIA CORPORATION

Inventor： Christian AMSINCK ,  Bengt-olaf SCHNEIDER ,  Jeffrey A. BOLZ

IPC: G06T1/60 ,  H04N19/44 ,  H04N19/136

CPC classification number: G06T1/60 ,  G06T15/005 ,  H04N19/436 ,  H04N19/593

Abstract: A raster operations (ROP) unit is configured to compress stencil values included in a stencil buffer. The ROP unit divides the stencil values into groups, subdivides each group into two halves, and selects an anchor value for each half. If the difference between each of the stencil values and the corresponding anchor lies within an offset range, and the difference between the two anchors lies within a delta range, then the group is compressible. For a compressible group, the ROP unit encodes the anchor value, offsets from anchors, and an anchor delta. This encoding enables the ROP unit to operate on the compressed group instead of the uncompressed stencil values, reducing the number of memory and computational operations associated with the stencil values. Consequently, the ROP unit reduces memory bandwidth use, reduces power consumption, and increases rendering rate compared to conventional ROP units that implement less flexible compression techniques.

Abstract translation: 光栅操作（ROP）单元被配置为压缩包括在模板缓冲器中的模板值。 ROP单元将模板值分成组，将每个组细分为两半，并为每个半部选择一个锚点值。 如果每个模板值和对应的锚点之间的差值在偏移范围内，并且两个锚点之间的差异位于增量范围内，那么该组是可压缩的。 对于可压缩组，ROP单元编码锚点值，与锚点的偏移量以及锚点三角形。 该编码使得ROP单元能够在压缩组而不是未压缩模板值上操作，从而减少与模板值相关联的存储器数量和计算操作。 因此，与实现较不灵活的压缩技术的传统ROP单元相比，ROP单元减少了内存带宽使用，降低了功耗，并提高了渲染速度。

公开(公告)号：US20140354634A1

公开(公告)日：2014-12-04

申请号：US13907711

申请日：2013-05-31

Applicant: Nvidia Corporation

Inventor： Christian AMSINCK ,  Eric B. LUM ,  Barry RODGERS ,  Tony LOUCA ,  Christian ROUET ,  Jonathan DUNAISKY

IPC: G06T17/10

CPC classification number: G06T15/405

Abstract: Updating depth related graphics data is described. Geometric primitives are processed. Pixels are generated from the primitives based on the processing, each of which has at least one corresponding depth value. Culling is performed on a first group of the pixels, based on a representation of the at least one depth related value corresponding to each. Pixels may be discarded based on the culling and upon which a second group of pixels remain. A depth related raster operations function is performed, in which data is transacted with a depth buffer. The culling function is updated in relation to the transacting. The updating is performed on the basis of a granularity, which characterizes the culling function.

Abstract translation: 描述更新深度相关图形数据。 几何图元被处理。 基于这些处理，从基元生成像素，每个处理具有至少一个对应的深度值。 基于对应于每个像素的至少一个深度相关值的表示，对第一组像素执行剔除。 可以基于剔除而丢弃像素，并且保留第二组像素。 执行深度相关的光栅操作功能，其中数据与深度缓冲器进行交互。 剔除功能与交易相关更新。 基于粒度来进行更新，其特征在于剔除功能。