公开(公告)号：US20140267366A1

公开(公告)日：2014-09-18

申请号：US14019344

申请日：2013-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jeffrey A. BOLZ ,  Mark J. KILGARD ,  Henry Packard MORETON ,  Rui M. BASTOS ,  Eric B. LUM

IPC: G06T11/00

CPC classification number: G06T15/503 ,  G06T11/203

Abstract: A graphics processing pipeline within a parallel processing unit (PPU) is configured to perform path rendering by generating a collection of graphics primitives that represent each path to be rendered. The graphics processing pipeline determines the coverage of each primitive at a number of stencil sample locations within each different pixel. Then, the graphics processing pipeline reduces the number of stencil samples down to a smaller number of color samples, for each pixel. The graphics processing pipeline is configured to modulate a given color sample associated with a given pixel based on the color values of any graphics primitives that cover the stencil samples from which the color sample was reduced. The final color of the pixel is determined by downsampling the color samples associated with the pixel.

Abstract translation: 并行处理单元（PPU）中的图形处理流水线被配置为通过生成表示要渲染的每个路径的图形基元的集合来执行路径渲染。 图形处理流水线确定每个不同像素内的多个模版样本位置上每个图元的覆盖范围。 然后，对于每个像素，图形处理管线将模板样本的数量减少到较少数量的颜色样本。 图形处理流水线被配置为基于覆盖颜色样本从其降低的模板样本的任何图形图元的颜色值来调制与给定像素相关联的给定颜色样本。 通过对与像素相关联的颜色样本进行下采样来确定像素的最终颜色。

公开(公告)号：US20140176589A1

公开(公告)日：2014-06-26

申请号：US13723078

申请日：2012-12-20

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, JR. ,  Ziyad S. Hakura ,  Henry Packard MORETON

IPC: G09G5/00

CPC classification number: G09G5/001 ,  G06T1/60 ,  G06T15/005

Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.

公开(公告)号：US20150170409A1

公开(公告)日：2015-06-18

申请号：US14106582

申请日：2013-12-13

Applicant: NVIDIA CORPORATION

Inventor： Yong HE ,  Eric B. LUM ,  Eric ENDERTON ,  Henry Packard MORETON ,  Kayvon FATAHALIAN

IPC: G06T15/80

CPC classification number: G06T15/80 ,  G06T15/005

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

Abstract translation: 本发明的一个实施例包括以可变粒度执行像素着色的并行处理单元（PPU）。 对于在像素块上以低频率变化的效果，粗调阴影单元对像素块中的像素的子集执行相关联的阴影操作。 相比之下，对于在像素块上的高频率变化的效果，精细着色单元对像素块中的每个像素执行相关联的阴影操作。 因为PPU实现了粗略的阴影单元和精细的阴影单元，PPU可以基于每个像素组的变化频率来调整每个效果的阴影效果。 相比之下，常规PPU通常计算每像素的所有效果，对低频效应执行冗余着色操作。 因此，为了产生类似的图像质量，与常规PPU相比，PPU消耗更少的功率并且增加渲染帧速率。

公开(公告)号：US20150170408A1

公开(公告)日：2015-06-18

申请号：US14106580

申请日：2013-12-13

Applicant: NVIDIA CORPORATION

Inventor： Yong HE ,  Eric B. LUM ,  Eric ENDERTON ,  Henry Packard MORETON ,  Kayvon FATAHALIAN

IPC: G06T15/80

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T15/00 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

公开(公告)号：US20150097847A1

公开(公告)日：2015-04-09

申请号：US14046064

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Jonathan DUNAISKY ,  Henry Packard MORETON ,  Jeffrey A. BOLZ ,  Yury Y. URALSKY ,  James Leroy DEMING ,  Rui M. BASTOS ,  Patrick R. BROWN ,  Amanpreet GREWAL ,  Christian AMSINCK ,  Poornachandra RAO ,  Jerome F. DULUK, JR. ,  Andrew J. TAO

IPC: G09G5/39 ,  G06T1/60

CPC classification number: G09G5/39 ,  G06F12/0897 ,  G06F12/1027 ,  G06T1/60

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

Abstract translation: 本发明的一个实施例包括被配置为管理稀疏映射的存储器管理单元（MMU）。 MMU根据指示稀疏状态的页表项（PTE）处理将虚拟地址转换为物理地址的请求。 如果MMU确定PTE不包括从虚拟地址到物理地址的映射，则MMU将根据稀疏状态对该请求进行响应。 如果稀疏状态为活动状态，则MMU将根据请求的类型是否为写入操作确定物理地址，然后生成请求的确认。 相比之下，如果稀疏状态不活动，则MMU会生成页面错误。 有利地，所公开的实施例使得计算机系统能够管理稀疏映射，而不会引起与页面故障和常规的基于软件的稀疏映射管理相关联的性能下降。

公开(公告)号：US20170132834A1

公开(公告)日：2017-05-11

申请号：US15411918

申请日：2017-01-20

Applicant: NVIDIA Corporation

Inventor： Yong HE ,  Eric B. LUM ,  Eric ENDERTON ,  Henry Packard MORETON ,  Kayvon FATAHALIAN

IPC: G06T15/80 ,  G06T15/00 ,  G06T1/20

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T15/00 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

公开(公告)号：US20140267264A1

公开(公告)日：2014-09-18

申请号：US13830106

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Cyril CRASSIN ,  Yury Y. URALSKY ,  Eric ENDERTON ,  Eric B. LUM ,  Jerome F. DULUK, JR. ,  Henry Packard MORETON ,  David LUEBKE

IPC: G06T15/08

CPC classification number: G06T15/08

Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves identifying a voxel that is intersected by a first graphics primitive that has a front side and a back side and selecting a plurality of sample points within the voxel. The technique further involves determining, for each sample point included in the plurality of sample points, whether the sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive. Finally, the technique involves storing, for at least a first sample point included in the plurality of sample points, a first result in a voxel mask reflecting whether the first sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive.

Abstract translation: 本发明的一个实施例提出了一种用于执行体素化的技术。 该技术涉及识别由具有前侧和后侧的第一图形基元相交并且在体素内选择多个采样点的体素。 该技术还涉及对于包括在多个采样点中的每个采样点，确定采样点是位于第一图形原语的前侧还是位于第一图形基元的背面。 最后，该技术涉及对于至少包括在多个采样点中的第一采样点存储体素掩模中的第一结果，反映第一采样点是第一采样点是位于第一图形原语的前侧还是位于后面 侧面的第一个图形原语。

公开(公告)号：US20140176588A1

公开(公告)日：2014-06-26

申请号：US13723015

申请日：2012-12-20

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, JR. ,  Ziyad S. Hakura ,  Henry Packard MORETON

IPC: G09G5/00

CPC classification number: G09G5/001 ,  G06T1/60 ,  G06T15/005

Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.

Abstract translation: 图形处理单元包括一组几何处理单元，每个几何处理单元被配置为彼此并行处理图形基元。 给定的几何处理单元生成一个或多个图形基元或几何对象并在本地缓冲相关联的顶点数据。 几何处理单元还将不同的索引集合缓冲到那些顶点，其中每个这样的集合表示不同的图形基元或几何对象。 然后，几何处理单元可以将缓冲的顶点和索引彼此并行地传送到全局缓冲器。 流输出同步单元通过向每个几何处理单元提供在可以写入顶点的全局顶点缓冲器内的不同基地址来协调顶点和索引的并行流。 流输出同步单元还为每个几何处理单元提供在可以写入索引的全局索引缓冲器内的不同基地址。

公开(公告)号：US20230084570A1

公开(公告)日：2023-03-16

申请号：US17946221

申请日：2022-09-16

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  Henry Packard MORETON ,  Yury URALSKY ,  Levi OLIVER ,  Magnus ANDERSSON ,  Johannes DELIGIANNIS

IPC: G06T15/06 ,  G06T17/20

Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask that defines visibility states for regions within a geometric primitive available to be accessed in the ray tracing hardware accelerator when a ray intersection is detected for the geometric primitive.

公开(公告)号：US20150084974A1

公开(公告)日：2015-03-26

申请号：US14033389

申请日：2013-09-20

Applicant: NVIDIA CORPORATION

Inventor： Eric B. LUM ,  Cass W. EVERITT ,  Henry Packard MORETON ,  Yury Y. URALSKY ,  Cyril CRASSIN ,  Jerome F. DULUK, Jr.

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60

Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.

Abstract translation: 一个实施例提出了一种用于将存储器分配给表面的方法。 软件应用程序指定表面数据，包括交错状态数据。 基于交错状态数据，表面访问单元使得与表面相关联的离散坐标导出的地址变得膨胀，从而产生具有与数据不对应的可预测地址模式的膨胀的虚拟地址空间。 有利地，通过创建不对应于数据的地址的可预测区域，软件应用程序可以配置表面以与一个或多个其他表面共享物理存储器空间。 特别地，软件应用程序可以将虚拟地址空间与对应于互补数据模式的一个或多个虚拟地址空间映射到相同的物理基址。 并且，通过将虚拟地址空间重叠到物理地址空间中的相同页面上，与使用现有技术的分配技术相比，物理存储器可能更加密集。