公开(公告)号：US08704826B1

公开(公告)日：2014-04-22

申请号：US14023309

申请日：2013-09-10

Applicant: Nvidia Corporation

Inventor： Ziyad S. Hakura ,  Robert Ohannessian ,  Cynthia Allison ,  Dale L. Kirkland

IPC: G06T15/00 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes approaches for processing graphics primitives associated with cache tiles when rendering an image. A set of graphics primitives associated with a first render target configuration is received from a first portion of a graphics processing pipeline, and the set of graphics primitives is stored in a memory. A condition is detected indicating that the set of graphics primitives is ready for processing, and a cache tile is selected that intersects at least one graphics primitive in the set of graphics primitives. At least one graphics primitive in the set of graphics primitives that intersects the cache tile is transmitted to a second portion of the graphics processing pipeline for processing. One advantage of the disclosed embodiments is that graphics primitives and associated data are more likely to remain stored on-chip during cache tile rendering, thereby reducing power consumption and improving rendering performance.

Abstract translation: 本发明的一个实施例包括在渲染图像时处理与高速缓存拼贴相关联的图形图元的方法。 从图形处理流水线的第一部分接收与第一渲染目标配置相关联的一组图形基元，并且将该组图形基元存储在存储器中。 检测到指示图形基元集合准备好进行处理的条件，并且选择与该组图形基元中的至少一个图形基元相交的高速缓存片。 与高速缓存片相交的图形基元组中的至少一个图形原语被传送到图形处理流水线的第二部分进行处理。 所公开的实施例的一个优点是图形原语和相关联的数据在高速缓存图块呈现期间更可能保持在芯片上，从而降低功耗并提高渲染性能。

公开(公告)号：US10147222B2

公开(公告)日：2018-12-04

申请号：US14952390

申请日：2015-11-25

Applicant: NVIDIA CORPORATION

Inventor： Ziyad Hakura ,  Cynthia Allison ,  Dale Kirkland ,  Jeffrey Bolz ,  Yury Uralsky ,  Jonah Alben

IPC: G06T17/00 ,  G06T15/00 ,  G06T15/40 ,  G06T15/50 ,  G06T15/80 ,  G06T17/20 ,  G06T1/20

Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.

公开(公告)号：US09336002B2

公开(公告)日：2016-05-10

申请号：US13967233

申请日：2013-08-14

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. Hakura ,  Pierre Souillot ,  Cynthia Allison ,  Dale L. Kirkland

IPC: G06T1/60 ,  G06F9/38 ,  G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/08 ,  G06F9/44 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a method for performing a multi-pass tiling test. The method includes combining a plurality of bounding boxes to generate a coarse bounding box. The method further includes identifying a first cache tile associated with a render surface and determining that the coarse bounding box intersects the first cache tile. The method further includes comparing each bounding box included in the plurality of bounding boxes against the first cache tile to determine that a first set of one or more bounding boxes included in the plurality of bounding boxes intersects the first cache tile. Finally, the method includes, for each bounding box included in the first set of one or more bounding boxes, processing one or more graphics primitives associated with the bounding box. One advantage of the disclosed technique is that the number of intersection calculations performed for each cache tile is reduced.

Abstract translation: 本发明的一个实施例包括执行多遍平铺测试的方法。 该方法包括组合多个边界框以产生粗略边界框。 该方法还包括识别与渲染表面相关联的第一高速缓存片段，并确定粗边界框与第一高速缓存片段相交。 该方法还包括将包含在多个边界框中的每个边界框与第一高速缓存块进行比较，以确定包含在多个边界框中的一个或多个边界框的第一组与第一高速缓存块相交。 最后，对于包含在一个或多个边界框的第一组中的每个边界框，该方法包括处理与边界框相关联的一个或多个图形基元。 所公开的技术的一个优点是减少了针对每个高速缓存平铺执行的交叉点计算的数量。

公开(公告)号：US10430989B2

公开(公告)日：2019-10-01

申请号：US14952400

申请日：2015-11-25

Applicant: NVIDIA CORPORATION

Inventor： Ziyad Hakura ,  Cynthia Allison ,  Dale Kirkland ,  Jeffrey Bolz ,  Yury Uralsky ,  Jonah Alben

IPC: G06T17/00 ,  G06T15/00 ,  G06T11/40

Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.

公开(公告)号：US09342311B2

公开(公告)日：2016-05-17

申请号：US13967195

申请日：2013-08-14

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. Hakura ,  Pierre Souillot ,  Cynthia Allison ,  Dale L. Kirkland ,  Rouslan Dimitrov

IPC: G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06T15/40 ,  G06T1/60 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/08 ,  G06F9/44 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a method for generating accumulated bounding boxes for graphics primitives. The method includes generating a first bounding box associated with a first graphics primitive. The method further includes, for each graphics primitive included in a first set of one or more additional graphics primitives, determining that the graphics primitive is within a threshold distance of the first bounding box, and adding the graphics primitive to the first bounding box. The method further includes determining not to add a second graphics primitive to the first bounding box. The method further includes generating a second bounding box associated with the second graphics primitive. Finally, the method includes transmitting the first bounding box to a tiling unit via a crossbar. One advantage of the disclosed embodiments is that multiple bounding boxes are combined to generate an accumulated bounding box that is then transferred across the crossbar.

Abstract translation: 本发明的一个实施例包括用于产生用于图形基元的累加边界框的方法。 该方法包括生成与第一图形基元相关联的第一边界框。 该方法还包括对于包括在一个或多个附加图形基元的第一组中的每个图形原语，确定图形原语在第一边界框的阈值距离内，并且将图形基元添加到第一边界框。 该方法还包括确定不将第二图形基元添加到第一边界框。 该方法还包括生成与第二图形基元相关联的第二边界框。 最后，该方法包括经由横杆将第一边界箱发送到平铺单元。 所公开的实施例的一个优点是组合多个边界框以产生累积的边界框，然后将其跨越横杠传送。