公开(公告)号：US20190139269A1

公开(公告)日：2019-05-09

申请号：US16209895

申请日：2018-12-04

Applicant: NVIDIA Corporation

Inventor： Yury Y. URALSKY ,  Jonah M. ALBEN ,  Ankan BANERJEE ,  Gregory MASSAL ,  Thomas PETERSEN ,  Oleg KUZNETSOV ,  Eric B. LUM ,  Prakshep MEHTA

IPC: G06T11/00 ,  G06T11/40

Abstract: A raster unit is configured to generate different sample patterns for adjacent pixels within a given frame. In addition, the raster unit may adjust the sample patterns between frames. The raster unit includes an index unit that selects a sample pattern table for use with a current frame. For a given pixel, the index unit extracts a sample pattern from the selected sample pattern table. The extracted sample pattern is used to generate coverage information for the pixel. The coverage information for all pixels is then used to generate an image. The resultant image may then be filtered to reduce or remove artifacts induced by the changing of sample locations.

公开(公告)号：US20150084974A1

公开(公告)日：2015-03-26

申请号：US14033389

申请日：2013-09-20

Applicant: NVIDIA CORPORATION

Inventor： Eric B. LUM ,  Cass W. EVERITT ,  Henry Packard MORETON ,  Yury Y. URALSKY ,  Cyril CRASSIN ,  Jerome F. DULUK, Jr.

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60

Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.

Abstract translation: 一个实施例提出了一种用于将存储器分配给表面的方法。 软件应用程序指定表面数据，包括交错状态数据。 基于交错状态数据，表面访问单元使得与表面相关联的离散坐标导出的地址变得膨胀，从而产生具有与数据不对应的可预测地址模式的膨胀的虚拟地址空间。 有利地，通过创建不对应于数据的地址的可预测区域，软件应用程序可以配置表面以与一个或多个其他表面共享物理存储器空间。 特别地，软件应用程序可以将虚拟地址空间与对应于互补数据模式的一个或多个虚拟地址空间映射到相同的物理基址。 并且，通过将虚拟地址空间重叠到物理地址空间中的相同页面上，与使用现有技术的分配技术相比，物理存储器可能更加密集。

公开(公告)号：US20150015594A1

公开(公告)日：2015-01-15

申请号：US13942415

申请日：2013-07-15

Applicant: NVIDIA CORPORATION

Inventor： Eric B. LUM ,  Jerome F. DULUK, JR.

IPC: G06T1/60

CPC classification number: G06T1/60 ,  B41F15/34 ,  G06T11/40 ,  G06T15/005

Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.

公开(公告)号：US20140267366A1

公开(公告)日：2014-09-18

申请号：US14019344

申请日：2013-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jeffrey A. BOLZ ,  Mark J. KILGARD ,  Henry Packard MORETON ,  Rui M. BASTOS ,  Eric B. LUM

IPC: G06T11/00

CPC classification number: G06T15/503 ,  G06T11/203

Abstract: A graphics processing pipeline within a parallel processing unit (PPU) is configured to perform path rendering by generating a collection of graphics primitives that represent each path to be rendered. The graphics processing pipeline determines the coverage of each primitive at a number of stencil sample locations within each different pixel. Then, the graphics processing pipeline reduces the number of stencil samples down to a smaller number of color samples, for each pixel. The graphics processing pipeline is configured to modulate a given color sample associated with a given pixel based on the color values of any graphics primitives that cover the stencil samples from which the color sample was reduced. The final color of the pixel is determined by downsampling the color samples associated with the pixel.

Abstract translation: 并行处理单元（PPU）中的图形处理流水线被配置为通过生成表示要渲染的每个路径的图形基元的集合来执行路径渲染。 图形处理流水线确定每个不同像素内的多个模版样本位置上每个图元的覆盖范围。 然后，对于每个像素，图形处理管线将模板样本的数量减少到较少数量的颜色样本。 图形处理流水线被配置为基于覆盖颜色样本从其降低的模板样本的任何图形图元的颜色值来调制与给定像素相关联的给定颜色样本。 通过对与像素相关联的颜色样本进行下采样来确定像素的最终颜色。

公开(公告)号：US20140267318A1

公开(公告)日：2014-09-18

申请号：US13795693

申请日：2013-03-12

Applicant: NVIDIA CORPORATION

Inventor： Eric B. LUM ,  Justin COBB ,  Rui M. BASTOS ,  Christian ROUET

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/005

Abstract: A computer-implemented method for drawing graphical objects within a graphics processing pipeline is disclosed. The method includes determining that a bypass mode for a first primitive is a no-bypass mode. The method further includes rasterizing the first primitive to generate a first set of rasterization results. The method further includes generating a first set of colors for the first set of rasterization results via a pixel shader unit. The method further includes rasterizing a second primitive to generate a second set of rasterization results. The method further includes generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any processing operations on the second set of rasterization results. The method further includes transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further processing.

Abstract translation: 公开了一种用于在图形处理流水线内绘制图形对象的计算机实现的方法。 该方法包括确定第一原语的旁路模式是无旁路模式。 该方法还包括光栅化第一原语以产生第一组光栅化结果。 该方法还包括经由像素着色器单元为第一组光栅化结果生成第一组颜色。 该方法还包括光栅化第二原语以生成第二组光栅化结果。 该方法还包括为第二组光栅化结果生成第二组颜色，而不使像素着色器单元对第二组光栅化结果执行任何处理操作。 该方法还包括将第一组像素颜色和第二组像素颜色传输到光栅操作（ROP）单元以用于进一步处理。

公开(公告)号：US20140267224A1

公开(公告)日：2014-09-18

申请号：US13802182

申请日：2013-03-13

Applicant: NVIDIA CORPORATION

Inventor： Eric B. LUM ,  Rui Bastos ,  Jerome F. Duluk, JR. ,  Henry Packard Moreton ,  Yury Y. Uralsky

IPC: G06T15/00

CPC classification number: G06T15/00 ,  G06T15/005 ,  G06T15/405

Abstract: Techniques are disclosed for storing post-z coverage data in a render target. A color raster operations (CROP) unit receives a coverage mask associated with a portion of a graphics primitive, where the graphics primitive intersects a pixel that includes a multiple samples, and the portion covers at least one sample. The CROP unit stores the coverage mask in a data field in the render target at a location associated with the pixel. One advantage of the disclosed techniques is that the GPU computes color and other pixel information only for visible fragments as determined by post-z coverage data. The GPU does not compute color and other pixel information for obscured fragments, thereby reducing overall power consumption and improving overall render performance.

Abstract translation: 公开了用于将z后覆盖数据存储在渲染目标中的技术。 颜色光栅操作（CROP）单元接收与图形基元的一部分相关联的覆盖掩模，其中图形基元与包括多个样本的像素相交，并且该部分覆盖至少一个样本。 CROP单元将覆盖掩码存储在与像素相关联的位置的渲染目标中的数据字段中。 所公开技术的一个优点是，GPU仅通过后z覆盖数据确定的可见片段计算颜色和其他像素信息。 GPU不会为模糊片段计算颜色和其他像素信息，从而降低总体功耗并改善整体渲染性能。

公开(公告)号：US20170132834A1

公开(公告)日：2017-05-11

申请号：US15411918

申请日：2017-01-20

Applicant: NVIDIA Corporation

Inventor： Yong HE ,  Eric B. LUM ,  Eric ENDERTON ,  Henry Packard MORETON ,  Kayvon FATAHALIAN

IPC: G06T15/80 ,  G06T15/00 ,  G06T1/20

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T15/00 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

公开(公告)号：US20160350965A1

公开(公告)日：2016-12-01

申请号：US14726381

申请日：2015-05-29

Applicant: NVIDIA CORPORATION

Inventor： Eric B. LUM ,  Justin COBB

IPC: G06T15/20 ,  G06T17/20 ,  G06T19/00

CPC classification number: G06T15/005 ,  G06T11/40

Abstract: One embodiment of the present invention includes a method for rendering a geometry object in a computer-generated scene. A screen space associated with a display screen is divided into a set of regions. For each region; a first sampling factor in a horizontal dimension is computed that represents a horizontal sampling factor for pixels located in the region, a second sampling factor in a vertical dimension is computed that represents a vertical sampling factor for the pixels located in the region, a first offset in the horizontal dimension is computed that represents a horizontal position associated with the region, and a second offset in the vertical dimension is computed that represent a vertical position associated with the region. When the geometry object is determined to intersect more than one region, an instance of the geometry object is generated each region that the geometry object intersects.

Abstract translation: 本发明的一个实施例包括用于在计算机生成的场景中渲染几何对象的方法。 与显示屏相关联的屏幕空间被划分为一组区域。 对于每个地区; 计算水平维度中的第一采样因子，其表示位于该区域中的像素的水平采样因子，计算垂直维度中的第二采样因子，其表示位于该区域中的像素的垂直采样因子，第一偏移 在水平维度中计算出水平尺寸，其表示与该区域相关联的水平位置，并且计算垂直维度中的第二偏移量，该第二偏移量表示与该区域相关联的垂直位置。 当几何对象被确定为与多个区域相交时，几何对象的实例将生成几何对象相交的每个区域。

公开(公告)号：US20150022519A1

公开(公告)日：2015-01-22

申请号：US13947745

申请日：2013-07-22

Applicant: Nvidia Corporation

Inventor： Eric B. LUM ,  Justin COBB ,  Barry N. RODGERS

IPC: G06T17/20

CPC classification number: G06T17/05

Abstract: One embodiment includes determining a first z-range for a first portion of a coarse raster tile, where the first portion includes a plurality of pixels having a first set of pixel locations, retrieving from a memory a corresponding z-range related to a second set of pixel locations associated with the coarse raster tile, where the first set of pixel locations comprises a subset of the second set of pixel locations, and comparing the first z-range to the corresponding z-range to determine whether the plurality of pixels is occluded. If the plurality of pixels determined to be occluded, then the plurality of pixels is culled. If the plurality of pixels is determined to not be occluded, then the plurality of pixels is transmitted to a fine raster unit for further processing. The coarse raster tile comprises a plurality of portions, including the first portion, and those portions are processed serially.

Abstract translation: 一个实施例包括确定粗光栅瓦片的第一部分的第一z范围，其中第一部分包括具有第一组像素位置的多个像素，从存储器检索与第二组相关的相应z范围 与所述粗略光栅瓦片相关联的像素位置，其中所述第一组像素位置包括所述第二组像素位置的子集，以及将所述第一z范围与所述对应的z范围进行比较，以确定所述多个像素是否被遮挡 。 如果多个像素被确定为被遮挡，则多个像素被剔除。 如果多个像素被确定为不被遮挡，则将多个像素发送到精细光栅单元以进行进一步处理。 粗光栅瓦片包括多个部分，包括第一部分，并且这些部分被串行处理。

公开(公告)号：US20140267382A1

公开(公告)日：2014-09-18

申请号：US13828752

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Walter R. STEINER ,  Eric B. LUM

IPC: G06T1/00

CPC classification number: G06T11/40

Abstract: One embodiment of the present invention sets forth a technique for improved rasterization of round points mapped into a tile space within a graphics processing pipeline. A set of candidate tiles are selected based on proximity to a round point. A tile within the set of candidate tiles may be rejected based on a rejection boundary. A tile may be rejected if no vertex associated with the tile is within the coverage area. Performance is improved by rejecting certain unneeded tiles that would otherwise be included in conventional rasterization. One embodiment advantageously enlists line drawing circuitry to determine whether a given tile intersects the coverage area.

Abstract translation: 本发明的一个实施例提出了一种用于改进映射到图形处理流水线内的瓦片空间的圆点的光栅化的技术。 基于与圆点的接近度来选择一组候选瓦片。 候选瓦片组内的瓦片可以基于拒绝边界被拒绝。 如果与瓦片相关联的顶点不在覆盖区域内，则瓦片可能被拒绝。 通过拒绝否则将包括在常规光栅化中的某些不需要的瓦片来改善性能。 一个实施例有利地引入线绘图电路以确定给定的瓦片是否与覆盖区域相交。