公开(公告)号：US20170132834A1

公开(公告)日：2017-05-11

申请号：US15411918

申请日：2017-01-20

Applicant: NVIDIA Corporation

Inventor： Yong HE ,  Eric B. LUM ,  Eric ENDERTON ,  Henry Packard MORETON ,  Kayvon FATAHALIAN

IPC: G06T15/80 ,  G06T15/00 ,  G06T1/20

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T15/00 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

公开(公告)号：US20140267264A1

公开(公告)日：2014-09-18

申请号：US13830106

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Cyril CRASSIN ,  Yury Y. URALSKY ,  Eric ENDERTON ,  Eric B. LUM ,  Jerome F. DULUK, JR. ,  Henry Packard MORETON ,  David LUEBKE

IPC: G06T15/08

CPC classification number: G06T15/08

Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves identifying a voxel that is intersected by a first graphics primitive that has a front side and a back side and selecting a plurality of sample points within the voxel. The technique further involves determining, for each sample point included in the plurality of sample points, whether the sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive. Finally, the technique involves storing, for at least a first sample point included in the plurality of sample points, a first result in a voxel mask reflecting whether the first sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive.

Abstract translation: 本发明的一个实施例提出了一种用于执行体素化的技术。 该技术涉及识别由具有前侧和后侧的第一图形基元相交并且在体素内选择多个采样点的体素。 该技术还涉及对于包括在多个采样点中的每个采样点，确定采样点是位于第一图形原语的前侧还是位于第一图形基元的背面。 最后，该技术涉及对于至少包括在多个采样点中的第一采样点存储体素掩模中的第一结果，反映第一采样点是第一采样点是位于第一图形原语的前侧还是位于后面 侧面的第一个图形原语。

公开(公告)号：US20140267266A1

公开(公告)日：2014-09-18

申请号：US13830173

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Cyril CRASSIN ,  Yury Y. URALSKY ,  Eric ENDERTON ,  Eric B. LUM ,  Jerome F. DULUK, JR. ,  Henry Packard MORETON ,  David LUEBKE

IPC: G06T15/08

CPC classification number: G06T15/08 ,  G06T17/00

Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a voxel is intersected by a first graphics primitive that has a front side and a back side and selecting one or more reference points within the voxel. The technique further involves, for each reference point, determining a distance from the reference point to the first graphics primitive and storing a first scalar value in an array based on the distance. The sign of the first scalar value reflects whether the reference point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive.

Abstract translation: 本发明的一个实施例提出了一种用于执行体素化的技术。 该技术涉及确定体素与具有前侧和后侧的第一图形原语相交并且选择体素内的一个或多个参考点。 该技术还涉及对于每个参考点，确定从参考点到第一图形基元的距离，并且基于该距离将第一标量值存储在阵列中。 第一标量值的符号反映参考点是位于第一图形图元的前侧还是位于第一图形基元的背面。

公开(公告)号：US20140267265A1

公开(公告)日：2014-09-18

申请号：US13830142

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Cyril CRASSIN ,  Yury Y. URALSKY ,  Eric ENDERTON ,  Eric B. LUM ,  Jerome F. DULUK, JR. ,  Henry Packard MORETON ,  David LUEBKE

IPC: G06T15/08

CPC classification number: G06T15/08

Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a first graphics primitive intersects a voxel and calculating a first set of coefficients associated with a first plane defined by the intersection of the first graphics primitive and the voxel. The technique further involves determining that a second graphics primitive intersects the voxel and calculating a second set of coefficients associated with a second plane defined by the intersection of the second graphics primitive and the voxel. The technique further involves calculating a third set of coefficients associated with a third surface based on the first set of coefficients and the second set of coefficients. The technique further involves calculating at least one of an amount of the voxel that is located on the back side of the third surface and an occlusion value based on the third set of coefficients.

Abstract translation: 本发明的一个实施例提出了一种用于执行体素化的技术。 该技术涉及确定第一图形基元与体元相交并且计算与由第一图形图元和体元的交点确定的第一平面相关联的第一组系数。 该技术还包括确定第二图形原语与体素相交并且计算与由第二图形图元和体元的交点定义的第二平面相关联的第二组系数。 该技术还涉及基于第一组系数和第二组系数来计算与第三表面相关联的第三组系数。 该技术还包括基于第三组系数来计算位于第三表面的背侧的体素的量中的至少一个和闭塞值。

公开(公告)号：US20240095996A1

公开(公告)日：2024-03-21

申请号：US17946509

申请日：2022-09-16

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  Eric ENDERTON ,  Nikhil DIXIT ,  Josh NOEL

IPC: G06T15/06

CPC classification number: G06T15/06

Abstract: To improve the efficiency of bounding volumes in a hardware based ray tracer, we employ a sheared axis-aligned bounding box to approximate an oriented bounding box typically defined by rotations. To achieve this, the bounding volume hierarchy builder shears an axis-aligned box to fit tightly around its enclosed oriented geometry in top level or bottom level space, then computes the inverse shear transform. The bounds are still stored as axis-aligned boxes in memory, now defined in the new sheared coordinate system, along with the derived parameters to transform a ray into the sheared coordinate system before testing intersection with the boxes. The ray-bounding volume intersection test is performed as usual, just in the new sheared coordinate system. Additional efficiencies are gained by constraining the number of shear dimensions, constraining the shear transform coefficients to a quantized list, sharing a shear transform across a collection of bounds, performing a shear transform only for ray-bounds testing and not for ray-geometry intersection testing, and adding a specialized shear transform calculator/accelerator to the hardware.

公开(公告)号：US20150170409A1

公开(公告)日：2015-06-18

申请号：US14106582

申请日：2013-12-13

Applicant: NVIDIA CORPORATION

Inventor： Yong HE ,  Eric B. LUM ,  Eric ENDERTON ,  Henry Packard MORETON ,  Kayvon FATAHALIAN

IPC: G06T15/80

CPC classification number: G06T15/80 ,  G06T15/005

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

Abstract translation: 本发明的一个实施例包括以可变粒度执行像素着色的并行处理单元（PPU）。 对于在像素块上以低频率变化的效果，粗调阴影单元对像素块中的像素的子集执行相关联的阴影操作。 相比之下，对于在像素块上的高频率变化的效果，精细着色单元对像素块中的每个像素执行相关联的阴影操作。 因为PPU实现了粗略的阴影单元和精细的阴影单元，PPU可以基于每个像素组的变化频率来调整每个效果的阴影效果。 相比之下，常规PPU通常计算每像素的所有效果，对低频效应执行冗余着色操作。 因此，为了产生类似的图像质量，与常规PPU相比，PPU消耗更少的功率并且增加渲染帧速率。

公开(公告)号：US20150170408A1

公开(公告)日：2015-06-18

申请号：US14106580

申请日：2013-12-13

Applicant: NVIDIA CORPORATION

Inventor： Yong HE ,  Eric B. LUM ,  Eric ENDERTON ,  Henry Packard MORETON ,  Kayvon FATAHALIAN

IPC: G06T15/80

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T15/00 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.