METHOD AND SYSTEM FOR TESTING A MEMORY
    1.
    发明申请
    METHOD AND SYSTEM FOR TESTING A MEMORY 有权
    用于测试存储器的方法和系统

    公开(公告)号:US20150058678A1

    公开(公告)日:2015-02-26

    申请号:US14066602

    申请日:2013-10-29

    CPC classification number: G11C29/08 G11C29/10

    Abstract: A method and system for testing a memory is provided in the present invention. The method includes the following steps. Each of at least one address bit to be tested of the memory is set to a fixed value. Current test data is written into memory unit(s) of the memory which the set address bit(s) correspond(s) to. Current read back data is read from the memory unit(s) which the set address bit(s) correspond(s) to. The current test data is compared with the current read back data. It is judged whether there is any signal integrity problem in unset address bit(s) of the memory according to the comparison result of the current test data and the current read back data, in order to determine fault address bit(s). The method and system for testing a memory provided by the present invention may determine fault address bit(s) of the memory simply and quickly.

    Abstract translation: 本发明提供了一种用于测试存储器的方法和系统。 该方法包括以下步骤。 将要测试的存储器的至少一个地址位中的每一个被设置为固定值。 当前的测试数据被写入存储器的存储器单元中,该存储器单元与设置的地址位相对应。 从设置的地址位对应的存储器单元读取当前的读回数据。 将当前的测试数据与当前的回读数据进行比较。 根据当前测试数据和当前读回数据的比较结果,判断存储器的未设定地址位是否存在任何信号完整性问题,以便确定故障地址位。 用于测试由本发明提供的存储器的方法和系统可以简单且快速地确定存储器的故障地址位。

    CIRCUIT BOARD AND POWER SOURCE MANAGEMENT SYSTEM OF CIRCUIT BOARD
    2.
    发明申请
    CIRCUIT BOARD AND POWER SOURCE MANAGEMENT SYSTEM OF CIRCUIT BOARD 有权
    电路板电路板和电源管理系统

    公开(公告)号:US20140132235A1

    公开(公告)日:2014-05-15

    申请号:US13791099

    申请日:2013-03-08

    CPC classification number: G06F1/26 H02M3/1584 H02M2001/0025

    Abstract: A power source management system of a circuit board that comprises: a processor, comprising a core voltage input terminal; and a core voltage feedback terminal; and a voltage regulating member, comprising a setting terminal with a fixed reference voltage provided thereto; a detecting terminal connected to the core voltage feedback terminal to detect a feedback core voltage from the core voltage feedback terminal; and a core voltage output terminal connected to the core voltage input terminal to provide a core voltage thereto, wherein the core voltage is regulated by the voltage regulating member based on the feedback core voltage, such that the feedback core voltage is equal to the fixed reference voltage, wherein an offset voltage equal to a difference between a desired core voltage of the processor and the fixed reference voltage is provided between the core voltage input terminal and the core voltage feedback terminal by the processor.

    Abstract translation: 一种电路板的电源管理系统,包括:处理器,包括核心电压输入端; 和核心电压反馈端子; 以及电压调节构件,包括具有固定参考电压的设定端子; 检测端子,连接到核心电压反馈端子,以检测来自核心电压反馈端子的反馈核心电压; 以及与核心电压输入端子连接以提供核心电压的核心电压输出端子,其中,基于反馈核心电压,电压调节部件对核心电压进行调节,使得反馈核心电压等于固定参考值 电压,其中由所述处理器在所述核心电压输入端子和所述核心电压反馈端子之间提供等于所述处理器的期望核心电压与所述固定参考电压之间的差的偏移电压。

    METHOD AND DEVICE FOR PROVIDING A GAME
    3.
    发明申请
    METHOD AND DEVICE FOR PROVIDING A GAME 有权
    提供游戏的方法和设备

    公开(公告)号:US20140051509A1

    公开(公告)日:2014-02-20

    申请号:US13667993

    申请日:2012-11-02

    Inventor: Fei Wang

    CPC classification number: G06F3/1454 A63F13/26 G09G2370/06 G09G2370/16

    Abstract: The present invention discloses a method and a device for providing a game. The method includes: a detection step, for determining an additional display device being attached to a mobile device; and a push step, for pushing multimedia information of the game to the additional display device to be presented by the additional display device, and pushing a visual human machine interface of the game to a display of the mobile device to be displayed by the display; wherein, a controlled object displayed on the additional display device is controlled by the visual human machine interface. The above-mentioned method and device for providing a game can make a game machine have a smaller size and be more portable, display multimedia information of a game on a bigger screen for players and provide players with a visual human machine interface on the entire screen of a mobile device, and therefore it improves user experiences.

    Abstract translation: 本发明公开了一种提供游戏的方法和装置。 该方法包括:检测步骤,用于确定附加到移动设备的附加显示设备; 以及推动步骤,用于将所述游戏的多媒体信息推送到所述附加显示装置以由所述附加显示装置呈现,以及将所述游戏的视觉人机界面推向要由所述显示器显示的所述移动装置的显示器; 其中,显示在附加显示装置上的受控对象由视觉人机界面控制。 上述用于提供游戏的方法和装置可以使游戏机具有更小的尺寸并且更便于携带,在玩家的较大屏幕上显示游戏的多媒体信息,并在整个屏幕上为玩家提供视觉人机界面 的移动设备,因此它改善了用户体验。

    Method and device for providing a game
    4.
    发明授权
    Method and device for providing a game 有权
    用于提供游戏的方法和设备

    公开(公告)号:US08858327B2

    公开(公告)日:2014-10-14

    申请号:US13667993

    申请日:2012-11-02

    Inventor: Fei Wang

    CPC classification number: G06F3/1454 A63F13/26 G09G2370/06 G09G2370/16

    Abstract: The present invention discloses a method and a device for providing a game. The method includes: a detection step, for determining an additional display device being attached to a mobile device; and a push step, for pushing multimedia information of the game to the additional display device to be presented by the additional display device, and pushing a visual human machine interface of the game to a display of the mobile device to be displayed by the display; wherein, a controlled object displayed on the additional display device is controlled by the visual human machine interface. The above-mentioned method and device for providing a game can make a game machine have a smaller size and be more portable, display multimedia information of a game on a bigger screen for players and provide players with a visual human machine interface on the entire screen of a mobile device, and therefore it improves user experiences.

    Abstract translation: 本发明公开了一种提供游戏的方法和装置。 该方法包括:检测步骤,用于确定附加到移动设备的附加显示设备; 以及推动步骤,用于将所述游戏的多媒体信息推送到所述附加显示装置以由所述附加显示装置呈现,以及将所述游戏的视觉人机界面推向要由所述显示器显示的所述移动装置的显示器; 其中,显示在附加显示装置上的受控对象由视觉人机界面控制。 上述用于提供游戏的方法和装置可以使游戏机具有更小的尺寸并且更便于携带,在玩家的较大屏幕上显示游戏的多媒体信息,并在整个屏幕上为玩家提供视觉人机界面 的移动设备,因此它改善了用户体验。

    Circuit board and power source management system of circuit board
    5.
    发明授权
    Circuit board and power source management system of circuit board 有权
    电路板电路板和电源管理系统

    公开(公告)号:US09436243B2

    公开(公告)日:2016-09-06

    申请号:US13791099

    申请日:2013-03-08

    CPC classification number: G06F1/26 H02M3/1584 H02M2001/0025

    Abstract: A power source management system of a circuit board that comprises: a processor, comprising a core voltage input terminal; and a core voltage feedback terminal; and a voltage regulating member, comprising a setting terminal with a fixed reference voltage provided thereto; a detecting terminal connected to the core voltage feedback terminal to detect a feedback core voltage from the core voltage feedback terminal; and a core voltage output terminal connected to the core voltage input terminal to provide a core voltage thereto, wherein the core voltage is regulated by the voltage regulating member based on the feedback core voltage, such that the feedback core voltage is equal to the fixed reference voltage, wherein an offset voltage equal to a difference between a desired core voltage of the processor and the fixed reference voltage is provided between the core voltage input terminal and the core voltage feedback terminal by the processor.

    Abstract translation: 一种电路板的电源管理系统,包括:处理器,包括核心电压输入端; 和核心电压反馈端子; 以及电压调节构件,包括具有固定参考电压的设定端子; 检测端子,连接到核心电压反馈端子,以检测来自核心电压反馈端子的反馈核心电压; 以及与核心电压输入端子连接以提供核心电压的核心电压输出端子,其中,基于反馈核心电压,电压调节部件对核心电压进行调节,使得反馈核心电压等于固定基准电压 电压,其中由所述处理器在所述核心电压输入端子和所述核心电压反馈端子之间提供等于所述处理器的期望核心电压与所述固定参考电压之间的差的偏移电压。

    Method and system for testing a memory
    6.
    发明授权
    Method and system for testing a memory 有权
    用于测试内存的方法和系统

    公开(公告)号:US09373416B2

    公开(公告)日:2016-06-21

    申请号:US14066602

    申请日:2013-10-29

    CPC classification number: G11C29/08 G11C29/10

    Abstract: A method and system for testing a memory is provided in the present invention. The method includes the following steps. Each of at least one address bit to be tested of the memory is set to a fixed value. Current test data is written into memory unit(s) of the memory which the set address bit(s) correspond(s) to. Current read back data is read from the memory unit(s) which the set address bit(s) correspond(s) to. The current test data is compared with the current read back data. It is judged whether there is any signal integrity problem in unset address bit(s) of the memory according to the comparison result of the current test data and the current read back data, in order to determine fault address bit(s). The method and system for testing a memory provided by the present invention may determine fault address bit(s) of the memory simply and quickly.

    Abstract translation: 本发明提供了一种用于测试存储器的方法和系统。 该方法包括以下步骤。 将要测试的存储器的至少一个地址位中的每一个被设置为固定值。 当前的测试数据被写入存储器的存储器单元中,该存储器单元与设置的地址位相对应。 从设置的地址位对应的存储器单元读取当前的读回数据。 将当前的测试数据与当前的回读数据进行比较。 根据当前测试数据和当前读回数据的比较结果,判断存储器的未设定地址位是否存在任何信号完整性问题,以便确定故障地址位。 用于测试由本发明提供的存储器的方法和系统可以简单且快速地确定存储器的故障地址位。

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