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公开(公告)号：US09436243B2
公开(公告)日：2016-09-06
申请号：US13791099
申请日：2013-03-08
申请人： NVIDIA CORPORATION
CPC分类号： G06F1/26 , H02M3/1584 , H02M2001/0025
摘要： A power source management system of a circuit board that comprises: a processor, comprising a core voltage input terminal; and a core voltage feedback terminal; and a voltage regulating member, comprising a setting terminal with a fixed reference voltage provided thereto; a detecting terminal connected to the core voltage feedback terminal to detect a feedback core voltage from the core voltage feedback terminal; and a core voltage output terminal connected to the core voltage input terminal to provide a core voltage thereto, wherein the core voltage is regulated by the voltage regulating member based on the feedback core voltage, such that the feedback core voltage is equal to the fixed reference voltage, wherein an offset voltage equal to a difference between a desired core voltage of the processor and the fixed reference voltage is provided between the core voltage input terminal and the core voltage feedback terminal by the processor.
摘要翻译： 一种电路板的电源管理系统，包括：处理器，包括核心电压输入端; 和核心电压反馈端子; 以及电压调节构件，包括具有固定参考电压的设定端子; 检测端子，连接到核心电压反馈端子，以检测来自核心电压反馈端子的反馈核心电压; 以及与核心电压输入端子连接以提供核心电压的核心电压输出端子，其中，基于反馈核心电压，电压调节部件对核心电压进行调节，使得反馈核心电压等于固定基准电压 电压，其中由所述处理器在所述核心电压输入端子和所述核心电压反馈端子之间提供等于所述处理器的期望核心电压与所述固定参考电压之间的差的偏移电压。
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公开(公告)号：US09373416B2
公开(公告)日：2016-06-21
申请号：US14066602
申请日：2013-10-29
申请人： NVIDIA Corporation
摘要： A method and system for testing a memory is provided in the present invention. The method includes the following steps. Each of at least one address bit to be tested of the memory is set to a fixed value. Current test data is written into memory unit(s) of the memory which the set address bit(s) correspond(s) to. Current read back data is read from the memory unit(s) which the set address bit(s) correspond(s) to. The current test data is compared with the current read back data. It is judged whether there is any signal integrity problem in unset address bit(s) of the memory according to the comparison result of the current test data and the current read back data, in order to determine fault address bit(s). The method and system for testing a memory provided by the present invention may determine fault address bit(s) of the memory simply and quickly.
摘要翻译： 本发明提供了一种用于测试存储器的方法和系统。 该方法包括以下步骤。 将要测试的存储器的至少一个地址位中的每一个被设置为固定值。 当前的测试数据被写入存储器的存储器单元中，该存储器单元与设置的地址位相对应。 从设置的地址位对应的存储器单元读取当前的读回数据。 将当前的测试数据与当前的回读数据进行比较。 根据当前测试数据和当前读回数据的比较结果，判断存储器的未设定地址位是否存在任何信号完整性问题，以便确定故障地址位。 用于测试由本发明提供的存储器的方法和系统可以简单且快速地确定存储器的故障地址位。
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3.发明授权System and method for modulating a duty cycle of a switching mode power supply 有权用于调制开关模式电源的占空比的系统和方法公开(公告)号：US09086707B2
公开(公告)日：2015-07-21
申请号：US13736943
申请日：2013-01-09
申请人： NVIDIA Corporation
发明人： Yu Zhao
CPC分类号： G05F1/10 , H02M3/157 , H02M3/1584
摘要： Disclosed are methods, devices, and systems to digitally control a duty cycle of a switching mode power supply. In one embodiment, a method comprises calculating a base duty cycle using a power management unit of a high-speed processing unit, calculating a dynamic offset duty cycle using the power management unit to apply a transfer function to a sampled feedback voltage signal, and adding the base duty cycle to the dynamic offset duty cycle to obtain a duty cycle of the switching mode power supply. A system comprises a switching mode power supply, a power management unit, a voltage sensor, and an analog to digital converter all embedded within a high-speed processing unit, and a pulse-width modulator coupled between the switching mode power supply and the high-speed processing unit to modulate the duty cycle of the switching mode power supply.
摘要翻译： 公开了用于数字控制开关模式电源的占空比的方法，装置和系统。 在一个实施例中，一种方法包括使用高速处理单元的功率管理单元来计算基本占空比，使用功率管理单元计算动态偏移占空比，以对采样的反馈电压信号施加传递函数，以及将 将基本占空比转换为动态偏移占空比，以获得开关模式电源的占空比。 系统包括全部嵌入在高速处理单元内的开关模式电源，电源管理单元，电压传感器和模数转换器，以及连接在开关模式电源和高电平之间的脉冲宽度调制器 速度处理单元来调制开关模式电源的占空比。
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公开(公告)号：US20150058678A1
公开(公告)日：2015-02-26
申请号：US14066602
申请日：2013-10-29
申请人： NVIDIA Corporation
IPC分类号： G06F11/22
摘要： A method and system for testing a memory is provided in the present invention. The method includes the following steps. Each of at least one address bit to be tested of the memory is set to a fixed value. Current test data is written into memory unit(s) of the memory which the set address bit(s) correspond(s) to. Current read back data is read from the memory unit(s) which the set address bit(s) correspond(s) to. The current test data is compared with the current read back data. It is judged whether there is any signal integrity problem in unset address bit(s) of the memory according to the comparison result of the current test data and the current read back data, in order to determine fault address bit(s). The method and system for testing a memory provided by the present invention may determine fault address bit(s) of the memory simply and quickly.
摘要翻译： 本发明提供了一种用于测试存储器的方法和系统。 该方法包括以下步骤。 将要测试的存储器的至少一个地址位中的每一个被设置为固定值。 当前的测试数据被写入存储器的存储器单元中，该存储器单元与设置的地址位相对应。 从设置的地址位对应的存储器单元读取当前的读回数据。 将当前的测试数据与当前的回读数据进行比较。 根据当前测试数据和当前读回数据的比较结果，判断存储器的未设定地址位是否存在任何信号完整性问题，以便确定故障地址位。 用于测试由本发明提供的存储器的方法和系统可以简单且快速地确定存储器的故障地址位。
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公开(公告)号：US20140132235A1
公开(公告)日：2014-05-15
申请号：US13791099
申请日：2013-03-08
申请人： NVIDIA CORPORATION
CPC分类号： G06F1/26 , H02M3/1584 , H02M2001/0025
摘要： A power source management system of a circuit board that comprises: a processor, comprising a core voltage input terminal; and a core voltage feedback terminal; and a voltage regulating member, comprising a setting terminal with a fixed reference voltage provided thereto; a detecting terminal connected to the core voltage feedback terminal to detect a feedback core voltage from the core voltage feedback terminal; and a core voltage output terminal connected to the core voltage input terminal to provide a core voltage thereto, wherein the core voltage is regulated by the voltage regulating member based on the feedback core voltage, such that the feedback core voltage is equal to the fixed reference voltage, wherein an offset voltage equal to a difference between a desired core voltage of the processor and the fixed reference voltage is provided between the core voltage input terminal and the core voltage feedback terminal by the processor.
摘要翻译： 一种电路板的电源管理系统，包括：处理器，包括核心电压输入端; 和核心电压反馈端子; 以及电压调节构件，包括具有固定参考电压的设定端子; 检测端子，连接到核心电压反馈端子，以检测来自核心电压反馈端子的反馈核心电压; 以及与核心电压输入端子连接以提供核心电压的核心电压输出端子，其中，基于反馈核心电压，电压调节部件对核心电压进行调节，使得反馈核心电压等于固定参考值 电压，其中由所述处理器在所述核心电压输入端子和所述核心电压反馈端子之间提供等于所述处理器的期望核心电压与所述固定参考电压之间的差的偏移电压。
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公开(公告)号：US09817455B2
公开(公告)日：2017-11-14
申请号：US13791322
申请日：2013-03-08
申请人： NVIDIA CORPORATION
发明人： Yu Zhao
CPC分类号： G06F1/26
摘要： The present invention provides a processor and a circuit board including the processor. The processor includes a data processing unit, and an external power supply component that is coupled to the data processing unit; wherein the data processing unit includes a power management unit that is integrated into the data processing unit, and the power management unit is used for performing power management for the data processing unit; and the power management unit further includes a pulse signal output terminal which is used for outputting a pulse-width modulation signal, and the pulse-width modulation signal controls the external power supply component to supply a stable operating voltage to the data processing unit. The present invention provides a processor with the improved performance, the improved stability and the simplified structure.
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