公开(公告)号：US11777483B1

公开(公告)日：2023-10-03

申请号：US17698867

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Nishit Harshad Shah ,  Ting Ku ,  Krishnamraju Kurra ,  Gunaseelan Ponnuvel ,  Tezaswi Raja ,  Suhas Satheesh

IPC: H03K5/24 ,  H03K19/20

CPC classification number: H03K5/24 ,  H03K19/20

Abstract: In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.

公开(公告)号：US11131711B1

公开(公告)日：2021-09-28

申请号：US16936264

申请日：2020-07-22

Applicant: NVIDIA Corporation

Inventor： Krishnamraju Kurra ,  Gunaseelan Ponnuvel ,  Divyesh Shah ,  Abhishek Akkur ,  Kartik Joshi ,  Tezaswi Raja ,  Andy Chamas

IPC: G01R31/00 ,  G01R31/317 ,  H01L27/02 ,  G01R31/3177 ,  H01L23/58

Abstract: In-chip decoupling capacitor circuits refer to decoupling capacitors (DCAPs) that are placed on a chip. These DCAPs are generally used to manage power supply noise for the chip, and can be utilized individually or as a distributed system. In some cases, DCAPs may make up a significant portion of the chip. Unfortunately, defects in DCAPs will degrade over time, will encroach into active logic, and will further cause automatic test pattern generation (ATPG) failure. To date, there has been a lack of structural test coverage for DCAP circuits, which reduces test coverage of the chip as a whole. To this end, defects on the chip as they relate to DCAPs (i.e. shorts in the DCAP) may not be detected. The present disclosure provides a structural test system and method for DCAPs and other passive logic components located on-chip.

公开(公告)号：US11619661B1

公开(公告)日：2023-04-04

申请号：US17698879

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Nishit Harshad Shah ,  Ting Ku ,  Krishnamraju Kurra ,  Gunaseelan Ponnuvel ,  Tezaswi Raja ,  Suhas Satheesh

IPC: G01R19/165 ,  G01R19/00 ,  G06F1/04 ,  H03K19/20

Abstract: In various embodiments, a current measurement circuit measures an input current within an integrated circuit. The current measurement circuit includes an integration capacitor, an operational amplifier, a comparison capacitor, an inverter, and multiple switches. The current measurement circuit is coupled to a clocking circuit that, during operation, generates a two-phase clock having a frequency that is proportional to the input current. At least a portion of the switches are turned on during a first phase of the two-phase clock and are turned off during a second phase of the two-phase clock.