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    ADAPTIVE VOLTAGE FREQUENCY SCALING FOR OPTIMAL POWER EFFICIENCY
    2.
    发明申请
    ADAPTIVE VOLTAGE FREQUENCY SCALING FOR OPTIMAL POWER EFFICIENCY 审中-公开

    公开(公告)号：US20180123604A1

    公开(公告)日：2018-05-03

    申请号：US15340901

    申请日：2016-11-01

    Applicant: NVIDIA CORPORATION

    Inventor： Tezaswi Raja ,  Ben Faulkner ,  Divya Ramakrishnan ,  Tao Liu ,  Veeramani V ,  Ayon Dey ,  Javid Aziz

    IPC: H03L7/099 ,  H03L1/00 ,  H03L5/00

    Abstract: Aspects of the present invention are directed to techniques for improving the efficiency of power supply schemes by continuously and adaptively scaling voltage and frequency levels in an integrated circuit based on measured conditions in real-time, without resorting to a reliance on excessive pre-computed margins typical of conventional schemes. Embodiments of the present invention employ a self-tuning dynamic voltage control oscillator (or other similar clock signal generator) that sets the frequency for components in the integrated circuit. When a requested frequency exceeds a maximum allowed frequency for a given voltage level (accounting for other age and temperature related conditions), a look-up table is dynamically referenced to determine a new voltage level that is sufficient to safely and efficiently generate the requested frequency. The look-up table continuously receives updates on the operating conditions, and new voltage requests can be generated dynamically as necessary based on the system's current needs.

    Supply-voltage control for device power management
    3.
    发明授权
    Supply-voltage control for device power management 有权

    公开(公告)号：US09939883B2

    公开(公告)日：2018-04-10

    申请号：US13728824

    申请日：2012-12-27

    Applicant: NVIDIA Corporation

    Inventor： Madhu Swarna ,  Tezaswi Raja

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/3228 ,  Y02D10/172 ,  Y02D50/20

    Abstract: One embodiment provides a method for reducing leakage current in device logic having an operational supply-voltage threshold, a nonzero data-retention supply-voltage threshold, and two or more on-die transistor switches to switchably connect a voltage source to the device logic. After the logic enters an idle period, one or more of the switches are opened to lower a supply voltage of the logic below the operational supply-voltage threshold but above the data-retention supply-voltage threshold. When the logic exits the idle period, one or more of the switches are closed to raise the supply voltage of the logic above the operational supply-voltage threshold.

    Degradation detector and method of detecting the aging of an integrated circuit
    4.
    发明授权
    Degradation detector and method of detecting the aging of an integrated circuit 有权
    降解检测器和集成电路老化检测方法

    公开(公告)号：US09494641B2

    公开(公告)日：2016-11-15

    申请号：US14163066

    申请日：2014-01-24

    Applicant: Nvidia Corporation

    Inventor： Brian Smith ,  Stephen Felix ,  Tezaswi Raja ,  Roman Surgutchik

    IPC: G01R31/28 ,  G01R31/317 ,  H03K3/03 ,  G01R1/30

    CPC classification number: G01R31/2858 ,  G01R1/30 ,  G01R31/2837 ,  G01R31/2851 ,  G01R31/31727 ,  H03K3/0315

    Abstract: A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

    Abstract translation: 用于集成电路（IC）的劣化检测器，检测IC中的老化的方法和结合了劣化检测器的IC或方法。 在一个实施例中，劣化检测器包括：（1）耦合到功率门和时钟门的离线环形振荡器（RO），（2）耦合到时钟门的冷冻RO，（3）在线RO和（4） ）分析器，其耦合到离线RO，冷冻RO和在线RO，并且可操作以将劣化检测器置于正常状态，其中脱机RO与驱动电压源和时钟源两者断开，冷冻RO连接 到驱动电压源但与时钟源断开，并且在线RO连接到驱动电压源和时钟源。

    System and method for providing low-voltage, self-powered voltage multi-sensing feedback
    5.
    发明授权
    System and method for providing low-voltage, self-powered voltage multi-sensing feedback 有权
    提供低压，自供电电压多感测反馈的系统和方法

    公开(公告)号：US09292065B2

    公开(公告)日：2016-03-22

    申请号：US14055790

    申请日：2013-10-16

    Applicant: NVIDIA Corporation

    Inventor： George Ferenc Kokai ,  Tezaswi Raja

    IPC: G06F1/26 ,  G05F1/46

    CPC classification number: G06F1/26 ,  G05F1/46 ,  G05F1/462

    Abstract: A system and method are provided for regulating a supply voltage of a device. The method includes the steps of determining whether a supply voltage for an analog multiplexor is below a threshold voltage. If the supply voltage for the analog multiplexor is below the threshold voltage, then the method includes the step of shorting the supply voltage to an output of the analog multiplexor. However, if the supply voltage for the analog multiplexor is above or equal to the threshold voltage, then the method includes the step of transmitting at least one input signal coupled to the analog multiplexor to the output of the analog multiplexor. A system configured to implement the method may include a power management integrated circuit configured to generate a supply voltage for a device and a device that includes a self-powered analog multiplexor with voltage sensing bypass switch.

    Abstract translation: 提供了一种用于调节装置的电源电压的系统和方法。 该方法包括以下步骤：确定模拟多路复用器的电源电压是否低于阈值电压。 如果模拟多路复用器的电源电压低于阈值电压，则该方法包括将模拟多路复用器的输出端的电源电压短路的步骤。 然而，如果模拟多路复用器的电源电压高于或等于阈值电压，则该方法包括将耦合到模拟多路复用器的至少一个输入信号发送到模拟多路复用器的输出的步骤。 被配置为实现该方法的系统可以包括电源管理集成电路，其被配置为产生用于设备的电源电压和包括具有电压感测旁路开关的自供电模拟多路复用器的设备。

    LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT FOR CLOCK SIGNAL HAVING PHASE-TO-PHASE VARIATION
    6.
    发明公开
    LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT FOR CLOCK SIGNAL HAVING PHASE-TO-PHASE VARIATION 审中-公开

    公开(公告)号：US20240340157A1

    公开(公告)日：2024-10-10

    申请号：US18295537

    申请日：2023-04-04

    Applicant: NVIDIA Corporation

    Inventor： Kedar Rajpathak ,  Tezaswi Raja

    IPC: H04L7/033 ,  H04L7/00

    CPC classification number: H04L7/0331 ,  H04L7/0008 ,  H04L7/0337

    Abstract: Circuitry and method of operating a circuit for monitoring a clock signal having phase-to-phase variation is disclosed. The method comprises adding a fixed number of bits to a pulse count of a reference phase instance for a high or low phase to yield a modified added pulse count when detecting a clock slow abnormality, subtracting the fixed number of bits from the pulse count of the reference phase instance to yield a modified subtracted pulse count when detecting a clock fast abnormality, comparing the modified added pulse count to a pulse count for an immediately subsequent phase instance of the high or low phase count of the clock signal when detecting the clock slow abnormality, and comparing the modified subtracted pulse count to the pulse count for the immediately subsequent phase instance of the high phase or low phase count of the clock signal when detecting the clock fast abnormality.

    On-die techniques for asynchnorously comparing voltages
    7.
    发明授权
    On-die techniques for asynchnorously comparing voltages 有权

    公开(公告)号：US11777483B1

    公开(公告)日：2023-10-03

    申请号：US17698867

    申请日：2022-03-18

    Applicant: NVIDIA CORPORATION

    Inventor： Nishit Harshad Shah ,  Ting Ku ,  Krishnamraju Kurra ,  Gunaseelan Ponnuvel ,  Tezaswi Raja ,  Suhas Satheesh

    IPC: H03K5/24 ,  H03K19/20

    CPC classification number: H03K5/24 ,  H03K19/20

    Abstract: In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.

    Efficient voltage sensing systems and methods
    10.
    发明授权
    Efficient voltage sensing systems and methods 有权

    公开(公告)号：US09983602B2

    公开(公告)日：2018-05-29

    申请号：US13731937

    申请日：2012-12-31

    Applicant: NVIDIA Corporation

    Inventor： Tezaswi Raja ,  Sagheer Ahmad

    IPC: G05F1/10 ,  G01R19/00 ,  G06F1/26

    CPC classification number: G05F1/10 ,  G06F1/26

    Abstract: Presented systems and methods can facilitate efficient voltage sensing and regulation. In one embodiment, a presented multiple point voltage sensing system includes Multiple point voltage sensing. Multi-point sensing is the scheme where voltage feedback from Silicon to the voltage regulator is an average from multiple points on the die. In one embodiment, multi-point sensing is done by placing multiple sense points across the partition/silicon and merging the sense traces from each sense point with balanced routing. In one embodiment, a presented multiple point voltage sensing system includes Virtual VDD Sensing with guaranteed non-floating feedback. In one exemplary implementation, Virtual VDD Sensing with guaranteed non-floating feedback allows more accurate sensing when a component is power gated off by removing the sensing results associated with the component.

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