公开(公告)号：US10990732B1

公开(公告)日：2021-04-27

申请号：US16777443

申请日：2020-01-30

Applicant: Nvidia Corporation

Inventor： Tezaswi Raja ,  Siddharth Saxena ,  Ben Faulkner ,  Sachin Idgunji ,  Vinayak Bhargav Srinath ,  Wen Yueh ,  Chad Plummer ,  Kartik Joshi

IPC: G06F30/3312 ,  G06F30/337 ,  G06F119/12 ,  G06F119/10 ,  G06F119/08

Abstract: Introduced herein is an improved technique of recovering system frequency margin via distributed CPMs. The introduced technique creates and distributes multiple sets of always sensitized critical path replicas across a chip and monitors them for timing failure. The introduced technique takes feedback from these critical path replicas and dynamically boosts the clock frequency of the chip to remove the margin. The introduced technique provides more accurate and more comprehensive coverage of a chip performance.

公开(公告)号：US11131711B1

公开(公告)日：2021-09-28

申请号：US16936264

申请日：2020-07-22

Applicant: NVIDIA Corporation

Inventor： Krishnamraju Kurra ,  Gunaseelan Ponnuvel ,  Divyesh Shah ,  Abhishek Akkur ,  Kartik Joshi ,  Tezaswi Raja ,  Andy Chamas

IPC: G01R31/00 ,  G01R31/317 ,  H01L27/02 ,  G01R31/3177 ,  H01L23/58

Abstract: In-chip decoupling capacitor circuits refer to decoupling capacitors (DCAPs) that are placed on a chip. These DCAPs are generally used to manage power supply noise for the chip, and can be utilized individually or as a distributed system. In some cases, DCAPs may make up a significant portion of the chip. Unfortunately, defects in DCAPs will degrade over time, will encroach into active logic, and will further cause automatic test pattern generation (ATPG) failure. To date, there has been a lack of structural test coverage for DCAP circuits, which reduces test coverage of the chip as a whole. To this end, defects on the chip as they relate to DCAPs (i.e. shorts in the DCAP) may not be detected. The present disclosure provides a structural test system and method for DCAPs and other passive logic components located on-chip.