公开(公告)号：US11619661B1

公开(公告)日：2023-04-04

申请号：US17698879

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Nishit Harshad Shah ,  Ting Ku ,  Krishnamraju Kurra ,  Gunaseelan Ponnuvel ,  Tezaswi Raja ,  Suhas Satheesh

IPC: G01R19/165 ,  G01R19/00 ,  G06F1/04 ,  H03K19/20

Abstract: In various embodiments, a current measurement circuit measures an input current within an integrated circuit. The current measurement circuit includes an integration capacitor, an operational amplifier, a comparison capacitor, an inverter, and multiple switches. The current measurement circuit is coupled to a clocking circuit that, during operation, generates a two-phase clock having a frequency that is proportional to the input current. At least a portion of the switches are turned on during a first phase of the two-phase clock and are turned off during a second phase of the two-phase clock.

公开(公告)号：US11494370B2

公开(公告)日：2022-11-08

申请号：US16826005

申请日：2020-03-20

Applicant: NVIDIA Corporation

Inventor： Sreedhar Narayanaswamy ,  Shantanu K. Sarangi ,  Hemalkumar Chandrakant Doshi ,  Hari Unni Krishnan ,  Gunaseelan Ponnuvel ,  Brian Lawrence Smith

IPC: G06F16/23 ,  G06F11/27 ,  G06F11/273

Abstract: Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.

公开(公告)号：US09207277B2

公开(公告)日：2015-12-08

申请号：US13663644

申请日：2012-10-30

Applicant: Nvidia Corporation

Inventor： Craig Nishizaki ,  Peter Hung ,  Gunaseelan Ponnuvel ,  Chien-Hsiung Peng

IPC: G06Q90/00 ,  G07C3/08 ,  G01D21/00 ,  G06M11/00 ,  G06Q50/04 ,  G01R31/28

CPC classification number: G01R31/2894 ,  G01D21/00 ,  G06M11/00 ,  G06Q50/04 ,  G06Q90/00 ,  G07C3/08 ,  Y02P90/30

Abstract: A wafer acceptance test (WAT) system and method that, in one embodiment, includes: (1) a saturation current WAT subsystem operable to generate a weighted standard deviation based on target NMOS and PMOS saturation currents and saturation current WAT results, (2) a wafer IC speed WAT subsystem operable to generate a speed performance probability distribution of wafer ICs based on the weighted standard deviation and speed WAT results, (3) a wafer IC power WAT subsystem operable to employ the speed WAT results and power WAT results to generate a power performance model of wafer ICs, and (4) a yield calculator operable to generate a power performance variance probability distribution of wafer ICs based on the power performance model and the power WAT results, and to employ the speed performance probability distribution and the power performance variance probability distribution to generate the yield forecast with respect to a target performance profile.

Abstract translation: 一种晶片验收测试（WAT）系统和方法，其在一个实施例中包括：（1）饱和电流WAT子系统，其可操作以基于目标NMOS和PMOS饱和电流和饱和电流WAT结果产生加权标准偏差;（2） 晶片IC速度WAT子系统可操作以基于加权的标准偏差和速度WAT产生晶片IC的速度性能概率分布结果;（3）可操作以使用速度WAT结果的晶片IC功率WAT子系统和功率WAT结果产生 晶片IC的功率性能模型，以及（4）可以基于功率性能模型和功率WAT产生晶片IC的功率性能方差概率分布的收益计算器，并且使用速度性能概率分布和功率 性能差异概率分布，以产生关于目标绩效概况的收益率预测。

公开(公告)号：US20140214342A1

公开(公告)日：2014-07-31

申请号：US13754781

申请日：2013-01-30

Applicant: NVIDIA CORPORATION

Inventor： Gunaseelan Ponnuvel ,  Keith Michael Katcher ,  Tsung-Chi Eddy Yang ,  Nerinder Singh

IPC: G01R31/28

CPC classification number: H01L22/14 ,  H01L22/20

Abstract: A system, method, and computer program product are provided for verifying sensitivity test program stability. A sensitivity test program including a set of tests is run on a plurality of integrated circuit die fabricated on a silicon wafer, where each test in the set of tests specifies a different set of operating parameters for structures within each integrated circuit die. Results of the sensitivity test program are received for each integrated circuit die and the results of the sensitivity test program are stored in shadow bins allocated within a memory, where each shadow bin corresponds to a different test in the set of tests. The results may be used to verify and optimize operating voltage and operating frequency of different tests in the production test program and wafer fabrication process sensitivity.

Abstract translation: 提供了一种用于验证灵敏度测试程序稳定性的系统，方法和计算机程序产品。 包括一组测试的灵敏度测试程序在制造在硅晶片上的多个集成电路芯片上运行，其中该组测试中的每个测试为每个集成电路管芯内的结构规定了不同的一组操作参数。 针对每个集成电路管芯接收灵敏度测试程序的结果，并将灵敏度测试程序的结果存储在分配在存储器内的影子箱中，其中每个影子箱对应于该组测试中的不同测试。 结果可用于验证和优化生产测试程序和晶圆制造工艺灵敏度中不同测试的工作电压和工作频率。

公开(公告)号：US20140125364A1

公开(公告)日：2014-05-08

申请号：US13667872

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Dushyant Narayen ,  Nerinder Singh ,  Gunaseelan Ponnuvel ,  Hemant Kumar ,  Luai Nasser ,  Craig Nishizaki

IPC: G01R31/26

CPC classification number: G01R31/3008

Abstract: An IDDQ test system and method that, in one embodiment,deg includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.

Abstract translation: 一种IDDQ测试系统和方法，在一个实施例中，deg包括1）经验提取子系统，可操作以产生用于给定半导体器件设计的IDDQ对温度模型; 2）自动测试设备（ATE）测试子系统，可操作以获得 以及实现给定半导体器件设计的特定半导体器件的测量温度（Tm）的测量IDDQ值（IDDQm），获得测量的IDDQ值（IDDQm）后5秒内获得的测量温度（Tm），以及3）缩放 子系统可操作以使用IDDQ对温度模型将测量温度（Tm）下的测量IDDQ值（IDDQm）缩放到期望温度（Td）下的补偿IDDQ值（IDDQc）。

公开(公告)号：US11131711B1

公开(公告)日：2021-09-28

申请号：US16936264

申请日：2020-07-22

Applicant: NVIDIA Corporation

Inventor： Krishnamraju Kurra ,  Gunaseelan Ponnuvel ,  Divyesh Shah ,  Abhishek Akkur ,  Kartik Joshi ,  Tezaswi Raja ,  Andy Chamas

IPC: G01R31/00 ,  G01R31/317 ,  H01L27/02 ,  G01R31/3177 ,  H01L23/58

Abstract: In-chip decoupling capacitor circuits refer to decoupling capacitors (DCAPs) that are placed on a chip. These DCAPs are generally used to manage power supply noise for the chip, and can be utilized individually or as a distributed system. In some cases, DCAPs may make up a significant portion of the chip. Unfortunately, defects in DCAPs will degrade over time, will encroach into active logic, and will further cause automatic test pattern generation (ATPG) failure. To date, there has been a lack of structural test coverage for DCAP circuits, which reduces test coverage of the chip as a whole. To this end, defects on the chip as they relate to DCAPs (i.e. shorts in the DCAP) may not be detected. The present disclosure provides a structural test system and method for DCAPs and other passive logic components located on-chip.

公开(公告)号：US09007079B2

公开(公告)日：2015-04-14

申请号：US13667872

申请日：2012-11-02

Applicant: Nvidia Corporation

Inventor： Dushyant Narayen ,  Nerinder Singh ,  Gunaseelan Ponnuvel ,  Hemant Kumar ,  Luai Nasser ,  Craig Nishizaki

IPC: G01R31/26 ,  G01R31/30

CPC classification number: G01R31/3008

Abstract: An IDDQ test system and method that, in one embodiment, includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.

Abstract translation: 一种IDDQ测试系统和方法，其在一个实施例中包括1）经验提取子系统，用于为给定的半导体器件设计产生IDDQ与温度模型，2）自动测试设备（ATE）测试子系统，可操作以获得测量的 以及实现给定半导体器件设计的特定半导体器件的测量温度（Tm）的IDDQ值（IDDQm），获得测量的IDDQ值（IDDQm）的5秒内获得的测量温度（Tm），以及3）缩放子系统 可操作以使用IDDQ对温度模型将测量温度（Tm）下的测量IDDQ值（IDDQm）缩放到所需温度（Td）下的补偿IDDQ值（IDDQc）。

公开(公告)号：US20140118021A1

公开(公告)日：2014-05-01

申请号：US13663591

申请日：2012-10-30

Applicant: NVIDIA CORPORATION

Inventor： Gunaseelan Ponnuvel

IPC: G01R31/26

CPC classification number: H01L22/14 ,  G01R31/2831 ,  H01L22/20

Abstract: A test system and method for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics in a wafer fabrication process. In one embodiment, the test system includes: (1) structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies over integrated circuit (IC) samples fabricated under different process conditions and (2) derating factor selection circuitry coupled to the structural at-speed ATE and configured to employ results of the structural at-speed tests to identify performance deterioration in the samples, the performance deterioration indicating the derating factor to be employed in a subsequent wafer fabrication process.

Abstract translation: 一种用于在晶片制造工艺中选择要应用于具有不同电特性的晶体管的比率的降额因子的测试系统和方法。 在一个实施例中，测试系统包括：（1）结构高速自动测试设备（ATE），其可操作以在不同工艺条件下制造的集成电路（IC）样本上以多个时钟频率迭代结构性的速度测试;（2） 耦合到结构速度ATE的降额因子选择电路，并且被配置为采用结构速度测试的结果来识别样品中的性能劣化，所述性能劣化指示在随后的晶片制造过程中采用的降额因子。

公开(公告)号：US11777483B1

公开(公告)日：2023-10-03

申请号：US17698867

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Nishit Harshad Shah ,  Ting Ku ,  Krishnamraju Kurra ,  Gunaseelan Ponnuvel ,  Tezaswi Raja ,  Suhas Satheesh

IPC: H03K5/24 ,  H03K19/20

CPC classification number: H03K5/24 ,  H03K19/20

Abstract: In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.

公开(公告)号：US11693753B2

公开(公告)日：2023-07-04

申请号：US16601900

申请日：2019-10-15

Applicant: NVIDIA Corporation

Inventor： Gunaseelan Ponnuvel ,  Ashish Karandikar

IPC: G06F11/27 ,  G06F11/07 ,  G06F1/3296 ,  G05D1/00 ,  G06F11/22 ,  G06F1/3225 ,  G11C29/50 ,  G01R31/30 ,  G06F11/263 ,  G01R31/52 ,  G06F11/30 ,  G06F11/10 ,  G01R31/3187 ,  G06F11/24

CPC classification number: G06F11/27 ,  G05D1/0055 ,  G05D1/0088 ,  G06F1/3296 ,  G06F11/076 ,  G06F11/0793 ,  G01R31/3004 ,  G01R31/3187 ,  G01R31/52 ,  G06F1/3225 ,  G06F11/1048 ,  G06F11/22 ,  G06F11/2236 ,  G06F11/24 ,  G06F11/263 ,  G06F11/3024 ,  G06F11/3062 ,  G11C29/50

Abstract: In various examples, permanent faults in hardware component(s) and/or connections to the hardware component(s) of a computing platform may be predicted before they occur using in-system testing. As a result of this prediction, one or more remedial actions may be determined to enhance the safety of the computing platform (e.g., an autonomous vehicle). A degradation rate of a performance characteristic associated with the hardware component may be determined, detected, and/or computed by monitoring values of performance characteristics over time using fault testing.