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公开(公告)号:US20240132083A1
公开(公告)日:2024-04-25
申请号:US18048952
申请日:2022-10-23
Applicant: NVIDIA Corporation
Inventor: Anitha Kalva , Jae Wu , Shantanu Sarangi , Sailendra Chadalavada , Milind Sonawane , Chen Fang , Abilash Nerallapally
IPC: B60W50/02
CPC classification number: B60W50/0205 , B60W2050/0044
Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.
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公开(公告)号:US12291219B2
公开(公告)日:2025-05-06
申请号:US18048952
申请日:2022-10-24
Applicant: NVIDIA Corporation
Inventor: Anitha Kalva , Jae Wu , Shantanu Sarangi , Sailendra Chadalavada , Milind Sonawane , Chen Fang , Abilash Nerallapally
Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.
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公开(公告)号:US20240227824A9
公开(公告)日:2024-07-11
申请号:US18048952
申请日:2022-10-24
Applicant: NVIDIA Corporation
Inventor: Anitha Kalva , Jae Wu , Shantanu Sarangi , Sailendra Chadalavada , Milind Sonawane , Chen Fang , Abilash Nerallapally
IPC: B60W50/02
CPC classification number: B60W50/0205 , B60W2050/0044
Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.
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