公开(公告)号：US20230143807A1

公开(公告)日：2023-05-11

申请号：US18084933

申请日：2022-12-20

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: A63B53/04

CPC classification number: A63B53/0475 ,  A63B53/0416 ,  A63B2053/0491

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

公开(公告)号：US11768241B2

公开(公告)日：2023-09-26

申请号：US18084933

申请日：2022-12-20

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G01R31/3187 ,  G06F13/16 ,  G11C29/16 ,  G01R31/3177 ,  G06Q10/087 ,  G01R31/319 ,  G01R31/3185 ,  G11C29/26

CPC classification number: G01R31/3187 ,  G01R31/3177 ,  G01R31/31917 ,  G01R31/318597 ,  G06F13/1668 ,  G06Q10/087 ,  G11C29/16 ,  G11C2029/2602

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

公开(公告)号：US11573269B2

公开(公告)日：2023-02-07

申请号：US17377245

申请日：2021-07-15

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G01R31/3187 ,  G01R31/3177 ,  G11C29/16 ,  G01R31/319 ,  G06F13/16 ,  G06Q10/08 ,  G11C29/26

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

公开(公告)号：US11424000B2

公开(公告)日：2022-08-23

申请号：US17133781

申请日：2020-12-24

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G11C29/00 ,  G11C29/32 ,  G06F9/30 ,  G11C29/16

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.

公开(公告)号：US12291219B2

公开(公告)日：2025-05-06

申请号：US18048952

申请日：2022-10-24

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jae Wu ,  Shantanu Sarangi ,  Sailendra Chadalavada ,  Milind Sonawane ,  Chen Fang ,  Abilash Nerallapally

IPC: B60W50/02 ,  B60W50/00

Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.

公开(公告)号：US20240227824A9

公开(公告)日：2024-07-11

申请号：US18048952

申请日：2022-10-24

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jae Wu ,  Shantanu Sarangi ,  Sailendra Chadalavada ,  Milind Sonawane ,  Chen Fang ,  Abilash Nerallapally

IPC: B60W50/02

CPC classification number: B60W50/0205 ,  B60W2050/0044

Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.

公开(公告)号：US20210341537A1

公开(公告)日：2021-11-04

申请号：US17377245

申请日：2021-07-15

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G01R31/3187 ,  G01R31/3177 ,  G06F13/16 ,  G06Q10/08 ,  G11C29/16 ,  G01R31/319

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

公开(公告)号：US20210151118A1

公开(公告)日：2021-05-20

申请号：US17133781

申请日：2020-12-24

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G11C29/32 ,  G06F9/30 ,  G11C29/16

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.

公开(公告)号：US10902933B2

公开(公告)日：2021-01-26

申请号：US16557615

申请日：2019-08-30

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jue Wu

IPC: G11C29/00 ,  G11C29/32 ,  G06F9/30 ,  G11C29/16

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.

公开(公告)号：US20240132083A1

公开(公告)日：2024-04-25

申请号：US18048952

申请日：2022-10-23

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jae Wu ,  Shantanu Sarangi ,  Sailendra Chadalavada ,  Milind Sonawane ,  Chen Fang ,  Abilash Nerallapally

IPC: B60W50/02

CPC classification number: B60W50/0205 ,  B60W2050/0044

Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.