公开(公告)号：US20180191349A1

公开(公告)日：2018-07-05

申请号：US15908242

申请日：2018-02-28

Applicant: NVIDIA Corporation

Inventor： John Michael Wilson ,  John W. Poulton ,  Matthew Rudolph Fojtik ,  Carl Thomas Gray

IPC: H03K19/0185

CPC classification number: H03K19/018528

Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.

公开(公告)号：US09672008B2

公开(公告)日：2017-06-06

申请号：US14948175

申请日：2015-11-20

Applicant: NVIDIA Corporation

Inventor： Benjamin Andrew Keller ,  Matthew Rudolph Fojtik ,  Brucek Kurdo Khailany

IPC: G11C7/00 ,  G06F5/06 ,  G11C7/22 ,  G11C8/16

CPC classification number: G06F5/06 ,  G06F2205/061 ,  G11C7/222 ,  G11C8/16 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.

公开(公告)号：US20170093403A1

公开(公告)日：2017-03-30

申请号：US14869759

申请日：2015-09-29

Applicant: NVIDIA Corporation

Inventor： John Michael Wilson ,  John W. Poulton ,  Matthew Rudolph Fojtik ,  Carl Thomas Gray

IPC: H03K19/0185

CPC classification number: H03K19/018528

Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.

公开(公告)号：US10164638B2

公开(公告)日：2018-12-25

申请号：US15908242

申请日：2018-02-28

Applicant: NVIDIA Corporation

Inventor： John Michael Wilson ,  John W. Poulton ,  Matthew Rudolph Fojtik ,  Carl Thomas Gray

IPC: H03K19/0175 ,  H03K19/0185

Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.

公开(公告)号：US09954527B2

公开(公告)日：2018-04-24

申请号：US14869759

申请日：2015-09-29

Applicant: NVIDIA Corporation

Inventor： John Michael Wilson ,  John W. Poulton ,  Matthew Rudolph Fojtik ,  Carl Thomas Gray

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/018528

Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.

公开(公告)号：US09667230B1

公开(公告)日：2017-05-30

申请号：US15078956

申请日：2016-03-23

Applicant: NVIDIA Corporation

Inventor： Matthew Rudolph Fojtik ,  Ilyas Elkin ,  Yanqing Zhang

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356113

Abstract: A method for operating a latch and a latch circuit are disclosed. The latch circuit comprises a storage sub-circuit, a propagation sub-circuit, and a shared clock-enabled transistor. The storage sub-circuit is configured to capture a level of an input signal when a clock signal transitions from first level to a second level and hold the captured level to generate an output signal while the clock signal is at the second level. The propagation sub-circuit is configured to enable a path through a blocking transistor to the shared clock-enabled supply node to propagate the captured level of the input signal to the storage sub-circuit. The shared clock-enabled transistor is configured to couple the shared clock-enabled supply node to a power supply while the clock signal is at the first level and decouple the shared clock-enabled supply node from the power supply while the clock signal is at the second level.

公开(公告)号：US20160148661A1

公开(公告)日：2016-05-26

申请号：US14948175

申请日：2015-11-20

Applicant: NVIDIA Corporation

Inventor： Benjamin Andrew Keller ,  Matthew Rudolph Fojtik ,  Brucek Kurdo Khailany

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G06F5/06 ,  G06F2205/061 ,  G11C7/222 ,  G11C8/16 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.

Abstract translation: 提供了一种用于可暂存双工FIFO的系统，方法和计算机程序产品。 将数据与第一时钟域的第一时钟信号同步地写入双端口存储器阵列的条目，并且在第一时钟域中生成增量信号。 增量信号被确定为在第二对接信号的边缘附近转变，其中第二时钟信号是可暂停的时钟信号。 第二时钟域的第二时钟信号的下一个边缘被延迟，并且将增量信号发送到第二时钟域并被发送。