公开(公告)号：US20220417176A1

公开(公告)日：2022-12-29

申请号：US17848088

申请日：2022-06-23

Applicant: NVIDIA Corporation

Inventor： Glenn Alan Dearth ,  Nan Jiang ,  Mark D. Hummel ,  Gregory Michael Thorson ,  Karan Gupta ,  Dane Thomas Mrazek ,  Eric Anderson ,  Larry Robert Dennison

IPC: H04L49/101 ,  H04L49/201 ,  H04L45/00 ,  H04L45/24 ,  H04L45/30 ,  H04L45/80

Abstract: A method is provided for operating a network switch comprising a plurality of input ports and a plurality of output ports. The method comprises receiving a first data packet received via a first input port and a second data packet received via a second input port to be delivered to an egress endpoint connected to a first output port, configuring a plurality of crossbar switch units arranged in a tiled architecture to pass the first data packet to the first output port via a primary path and pass the second data packet to the first output port via a secondary path, and transmitting the first data packet and the second data packet to the egress endpoint. The first data packet and the second data packet pass through the plurality of crossbar switch units simultaneously.

公开(公告)号：US20150149788A1

公开(公告)日：2015-05-28

申请号：US14092870

申请日：2013-11-27

Applicant: NVIDIA Corporation

Inventor： Karan Gupta ,  Brahmanandam Karuturi ,  Jay S. Huang

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F21/00 ,  G06F21/602

Abstract: A system, method, and computer program product are provided for implementing asymmetric AES-CBC (Advanced Encryption Standard-Cipher Block Chaining) channels usage between encryption and decryption of data. In operation, data to be written to memory is identified. In addition, the data is encrypted utilizing a first AES-CBC channel. Additionally, at least one of a plurality of AES-CBC channels is utilized to decrypt the data to achieve a determined performance target.

Abstract translation: 提供了一种系统，方法和计算机程序产品，用于在数据的加密和解密之间实现非对称AES-CBC（高级加密标准 - 密码块链接）通道的使用。 在操作中，识别要写入存储器的数据。 另外，使用第一AES-CBC信道对数据进行加密。 另外，使用多个AES-CBC信道中的至少一个来解密数据以实现确定的性能目标。

公开(公告)号：US20240356866A1

公开(公告)日：2024-10-24

申请号：US18137132

申请日：2023-04-20

Applicant: NVIDIA Corporation

Inventor： Karan Gupta ,  Dane Thomas Mrazek ,  Nan Jiang ,  Mukesh Chand Agarwal

IPC: H04L49/101 ,  H04L49/00 ,  H04L49/9047

CPC classification number: H04L49/101 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/9047

Abstract: A Dynamic Destination Selection (DDS) crossbar, system for routing a packet, and a switch are provided. An illustrative DDS crossbar includes one or more adaptive routing circuits to track destination credit and port availability at a time of dispatching a packet, group multiple destinations into super destination groups, perform dynamic destination routing within a super destination group, and use the destination credit and port availability for the super destination group at the time of receiving the packet to select an output destination for the packet.

公开(公告)号：US20240296875A1

公开(公告)日：2024-09-05

申请号：US18176836

申请日：2023-03-01

Applicant: NVIDIA Corporation

Inventor： Jason Golbus ,  Chad Parsons ,  Kirk Twardowski ,  Lalit Gupta ,  Jesse Wang ,  Ka Yun Lee ,  Amy Chen ,  Ramya Challa ,  Karan Gupta

IPC: G11C7/10 ,  G11C29/50

CPC classification number: G11C7/1048 ,  G11C7/1075 ,  G11C29/50004 ,  G11C29/50012 ,  G11C2029/5004

Abstract: The disclosure provides improvements for transmitting data between different voltage domains of an IC, such as a chip. The disclosure introduces a data transfer circuit that uses a multi-voltage RAM, referred to herein as MVRAM, for transmitting data across the different voltage domains. The MVRAM has multiple memory cells with write ports and read ports on different clock and voltage domains. Accordingly, a write operation can occur completely on the write domain voltage and the read operation can occur completely on the read domain voltage. In one example, the data transfer circuit includes: (1) write logic operating at a first operating voltage, (2) read logic operating at second operating voltage, and (3) a MVRAM with write ports that operate under the first operating voltage and read ports that operate under the second operating voltage.

公开(公告)号：US09274979B2

公开(公告)日：2016-03-01

申请号：US14092870

申请日：2013-11-27

Applicant: NVIDIA Corporation

Inventor： Karan Gupta ,  Brahmanandam Karuturi ,  Jay S. Huang

IPC: G06F12/14 ,  G06F21/00 ,  G06F21/60

CPC classification number: G06F12/1408 ,  G06F21/00 ,  G06F21/602

Abstract: A system, method, and computer program product are provided for implementing asymmetric AES-CBC (Advanced Encryption Standard-Cipher Block Chaining) channels usage between encryption and decryption of data. In operation, data to be written to memory is identified. In addition, the data is encrypted utilizing a first AES-CBC channel. Additionally, at least one of a plurality of AES-CBC channels is utilized to decrypt the data to achieve a determined performance target.

Abstract translation: 提供了一种系统，方法和计算机程序产品，用于在数据的加密和解密之间实现非对称AES-CBC（高级加密标准 - 密码块链接）通道的使用。 在操作中，识别要写入存储器的数据。 另外，使用第一AES-CBC信道对数据进行加密。 另外，使用多个AES-CBC信道中的至少一个来解密数据以实现确定的性能目标。

公开(公告)号：US09251557B2

公开(公告)日：2016-02-02

申请号：US13911014

申请日：2013-06-05

Applicant: NVIDIA Corporation

Inventor： Sarika Bhimkaran Khatod ,  Mark Ernest Van Nostrand ,  Karan Gupta

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06F12/0207

Abstract: A system, method, and computer program product for recovering from a memory underflow condition associated with generating video signals are disclosed. The method includes the steps of determining that a first counter is greater than a second counter, incrementing an address corresponding to a memory fetch request by an offset, and issuing the memory fetch request to a memory. The first counter represents a number of pixels that have been read by a display pipeline for a current frame and the second counter represents a number of pixels requested from a memory for the current frame.

Abstract translation: 公开了一种用于从与生成视频信号相关联的存储器下溢条件恢复的系统，方法和计算机程序产品。 该方法包括以下步骤：确定第一计数器大于第二计数器，通过偏移递增对应于存储器提取请求的地址，以及向存储器发出存储器提取请求。 第一计数器表示由当前帧的显示管道读取的像素数，而第二计数器表示从当前帧的存储器请求的像素数。

公开(公告)号：US20140362094A1

公开(公告)日：2014-12-11

申请号：US13911014

申请日：2013-06-05

Applicant: NVIDIA Corporation

Inventor： Sarika Bhimkaran Khatod ,  Mark Ernest Van Nostrand ,  Karan Gupta

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06F12/0207

Abstract: A system, method, and computer program product for recovering from a memory underflow condition associated with generating video signals are disclosed. The method includes the steps of determining that a first counter is greater than a second counter, incrementing an address corresponding to a memory fetch request by an offset, and issuing the memory fetch request to a memory. The first counter represents a number of pixels that have been read by a display pipeline for a current frame and the second counter represents a number of pixels requested from a memory for the current frame.

Abstract translation: 公开了一种用于从与生成视频信号相关联的存储器下溢条件恢复的系统，方法和计算机程序产品。 该方法包括以下步骤：确定第一计数器大于第二计数器，通过偏移递增对应于存储器提取请求的地址，以及向存储器发出存储器提取请求。 第一计数器表示由当前帧的显示管道读取的像素数，而第二计数器表示从当前帧的存储器请求的像素数。