公开(公告)号：US09678529B2

公开(公告)日：2017-06-13

申请号：US14475139

申请日：2014-09-02

Applicant: Nvidia Corporation

Inventor： Marcin Hlond ,  Peter Cumming

IPC: G06F1/00 ,  G06F1/08 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126

Abstract: One aspect of the disclosure provides a computer system. In one embodiment, the computer system comprises a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal at a clock frequency. The at least one processor is configured to receive the clock signal and to operate at a speed dependent on the clock frequency. The clock frequency controller is configured to receive efficiency information indicating a current efficiency of the at least one processor. The clock frequency controller is further configured to receive a request from the processor for a target number of processor instructions to be handled in a particular time period. The clock frequency controller is further configured to output a frequency control signal to the clock generator for controlling the clock frequency in dependence thereon.

公开(公告)号：US20160062390A1

公开(公告)日：2016-03-03

申请号：US14475139

申请日：2014-09-02

Applicant: Nvidia Corporation

Inventor： Marcin Hlond ,  Peter Cumming

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126

Abstract: One aspect of the disclosure provides a computer system. In one embodiment, the computer system comprises a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal at a clock frequency. The at least one processor is configured to receive the clock signal and to operate at a speed dependent on the clock frequency. The clock frequency controller is configured to receive efficiency information indicating a current efficiency of the at least one processor. The clock frequency controller is further configured to receive a request from the processor for a target number of processor instructions to be handled in a particular time period. The clock frequency controller is further configured to output a frequency control signal to the clock generator for controlling the clock frequency in dependence thereon.

Abstract translation: 本公开的一个方面提供一种计算机系统。 在一个实施例中，计算机系统包括时钟发生器，至少一个处理器和时钟频率控制器。 时钟发生器被配置为以时钟频率提供时钟信号。 至少一个处理器被配置为接收时钟信号并以取决于时钟频率的速度工作。 时钟频率控制器被配置为接收指示至少一个处理器的当前效率的效率信息。 时钟频率控制器还被配置为从处理器接收在特定时间段内要处理的目标数量的处理器指令的请求。 时钟频率控制器还被配置为将频率控制信号输出到时钟发生器，用于根据其控制时钟频率。

公开(公告)号：US20150113300A1

公开(公告)日：2015-04-23

申请号：US14059661

申请日：2013-10-22

Applicant: NVIDIA Corporation

Inventor： Peter Cumming ,  Stephen Felix

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3215 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: Disclosed herein is a computer system operating on a local power supply of finite capacity has a plurality of system components each connected to a voltage supply system to draw current for their operation. The computer system includes a measuring circuit connected to detect prevailing usage of the local power supply, for example, a battery. The supply system is connected to receive an indication from the measuring circuit of excessive usage and is adapted to reduce the available supply voltage to selected ones of the system components. Each system component is associated with a clock controller which selects a clock frequency for operation of a component in dependence on the available voltage supply. Also disclosed is a supply system for a computer device operating on a local power supply of finite capacity.

Abstract translation: 这里公开的是在有限容量的本地电源上操作的计算机系统具有多个系统组件，每个系统组件连接到电压供应系统以为其操作抽取电流。 计算机系统包括连接以检测本地电源（例如电池）的主要使用的测量电路。 供应系统被连接以接收来自测量电路的过度使用的指示，并且适于减小对所选择的系统组件的可用电源电压。 每个系统组件与时钟控制器相关联，时钟控制器根据可用的电压供应选择用于操作组件的时钟频率。 还公开了一种用于在有限容量的本地电源上工作的计算机设备的供应系统。