公开(公告)号：US20200082254A1

公开(公告)日：2020-03-12

申请号：US16686931

申请日：2019-11-18

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/063 ,  G06N3/04 ,  G06F7/523 ,  G06F7/544

Abstract: A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. A first vector comprising only non-zero weight values and first associated positions of the non-zero weight values within a 3D space is received. A second vector comprising only non-zero input activation values and second associated positions of the non-zero input activation values within a 2D space is received. The non-zero weight values are multiplied with the non-zero input activation values, within a multiplier array, to produce a third vector of products. The first associated positions are combined with the second associated positions to produce a fourth vector of positions, where each position in the fourth vector is associated with a respective product in the third vector. The products in the third vector are transmitted to adders in an accumulator array, based on the position associated with each one of the products.

公开(公告)号：US10096134B2

公开(公告)日：2018-10-09

申请号：US15422359

申请日：2017-02-01

Applicant: NVIDIA Corporation

Inventor： Zhou Yan ,  Franciscus Wilhelmus Sijstermans ,  Yuanzhi Hua ,  Xiaojun Wang ,  Jeffrey Michael Pool ,  William J. Dally ,  Liang Chen

IPC: H03M7/00 ,  G06T9/00 ,  G06T1/20 ,  G06T1/60

Abstract: A method, computer program product, and system for sparse convolutional neural networks that improves efficiency is described. Multi-bit data for input to a processing element is received at a compaction engine. The multi-bit data is determined to equal zero and a single bit signal is transmitted from the memory interface to the processing element in lieu of the multi-bit data, where the single bit signal indicates that the multi-bit data equals zero. A compacted data sequence for input to a processing element is received by a memory interface. The compacted data sequence is transmitted from the memory interface to an expansion engine. Non-zero values are extracted from the compacted data sequence and zeros are inserted between the non-zero values by the expansion engine to generate an expanded data sequence that is output to the processing element.

公开(公告)号：US20180046900A1

公开(公告)日：2018-02-15

申请号：US15659371

申请日：2017-07-25

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/04 ,  G06F17/11

CPC classification number: G06N3/0427 ,  G06F9/28 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3555 ,  G06F9/3851 ,  G06F9/3887 ,  G06F17/11 ,  G06F17/16 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/082

Abstract: A method, computer program product, and system perform computations using a processor. A first instruction including a first index vector operand and a second index vector operand is received and the first index vector operand is decoded to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array. The second index vector operand is decoded to produce second coordinate sets for a second array, each second coordinate set including at least a third coordinate and a fourth coordinate of a position of a non-zero element in the second array. The first coordinate sets are summed with the second coordinate sets to produce output coordinate sets and the output coordinate sets are converted into a set of linear indices.

公开(公告)号：US09886409B2

公开(公告)日：2018-02-06

申请号：US14715394

申请日：2015-05-18

Applicant: NVIDIA Corporation

Inventor： Stephen William Keckler ,  William J. Dally ,  Steven Lee Scott ,  Brucek Kurdo Khailany ,  Michael Allen Parker

IPC: G06F17/50 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/409 ,  G06F13/1668 ,  G06F13/4068 ,  G06F17/5054

Abstract: An integrated circuit device comprises pin resources, a memory controller circuit, a network interface controller circuit, and transmitter circuitry. The pin resources comprise pads coupled to off-chip pins of the integrated circuit device. The memory controller circuit comprises a first interface and the network interface controller circuit comprises a second interface. The transmitter circuitry is configurable to selectively couple either a first signal of the first interface or a second signal of the second interface to a first pad of the pin resources based on a pin distribution between the first interface and the second interface.

公开(公告)号：US20170212857A1

公开(公告)日：2017-07-27

申请号：US14715394

申请日：2015-05-18

Applicant: NVIDIA Corporation

Inventor： Stephen William Keckler ,  William J. Dally ,  Steven Lee Scott ,  Brucek Kurdo Khailany ,  Michael Allen Parker

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/409 ,  G06F13/1668 ,  G06F13/4068 ,  G06F17/5054

Abstract: An integrated circuit device comprises pin resources, a memory controller circuit, a network interface controller circuit, and transmitter circuitry. The pin resources comprise pads coupled to off-chip pins of the integrated circuit device. The memory controller circuit comprises a first interface and the network interface controller circuit comprises a second interface. The transmitter circuitry is configurable to selectively couple either a first signal of the first interface or a second signal of the second interface to a first pad of the pin resources based on a pin distribution between the first interface and the second interface.

公开(公告)号：US09660599B2

公开(公告)日：2017-05-23

申请号：US14705838

申请日：2015-05-06

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H04K1/10 ,  H04L27/00 ,  H03F3/217 ,  H04B1/04 ,  H04L27/34 ,  H03K3/45 ,  H03F1/56 ,  H03F3/193 ,  H03F3/24

CPC classification number: H03F3/2175 ,  H03F1/565 ,  H03F3/193 ,  H03F3/24 ,  H03F3/245 ,  H03F2200/171 ,  H03F2200/387 ,  H03K3/45 ,  H03K2005/00052 ,  H04B1/04 ,  H04B2001/0408 ,  H04L27/3411

Abstract: A system and method are provided for controlling a radio frequency (RF) power amplifier. A magnitude input and a phase input are received for transmission of a RF signal by the RF power amplifier. A digital pulse, having a center position relative to an edge of a reference clock based on the phase input and having a width based on the magnitude input, is generated. The digital pulse is filtered with a resonant matching network to produce the RF signal corresponding to the magnitude input and the phase input.

公开(公告)号：US09389617B2

公开(公告)日：2016-07-12

申请号：US13770975

申请日：2013-02-19

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H02M3/158 ,  G05F1/10 ,  G01R27/14 ,  H02M3/156 ,  G06F1/30 ,  H02M1/00

CPC classification number: G05F1/10 ,  G01R27/14 ,  G06F1/305 ,  H02M3/156 ,  H02M3/1582 ,  H02M2001/0009

Abstract: A system and method are provided for sensing current. A current source is configured to generate a current and a pulsed sense enable signal is generated. A sense voltage across a resistive sense mechanism is sampled according to the sense enable signal, where the sense voltage represents a measurement of the current. A system includes the current source and a current sensing unit. The current source is configured to generate a current. The current sensing unit is coupled the current source and is configured to generate a pulsed sense enable signal and sample the sense voltage across a resistive sense mechanism according to the pulsed sense enable signal.

Abstract translation: 提供了一种感测电流的系统和方法。 电流源被配置为产生电流并且产生脉冲检测使能信号。 根据感测使能信号对电阻感测机构两端的感测电压进行采样，其中感测电压表示电流的测量。 系统包括电流源和电流感测单元。 当前源被配置为生成电流。 电流感测单元耦合电流源，并被配置为产生脉冲感测使能信号，并根据脉冲感测使能信号在电阻感测机构上采样感测电压。

公开(公告)号：US09231477B2

公开(公告)日：2016-01-05

申请号：US13868969

申请日：2013-04-23

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G05F1/00 ,  H02M3/158

CPC classification number: H02M3/1588 ,  H02M3/1584 ,  Y02B70/1466

Abstract: A system and method are provided for controlling a soft-switched modified buck regulator circuit. A voltage (Vx) across or a current through a pull-down switching mechanism within the modified buck regulator circuit is sensed when the pull-down switching mechanism is enabled, where the pull-down switching mechanism is coupled to an upstream end of an inductor and is coupled in parallel with a capacitor. A target time when the pull-down switching mechanism will be disabled (tlf) is computed and the pull-down transistor is disabled at the computed target time.

Abstract translation: 提供了一种用于控制软开关改进的降压调节器电路的系统和方法。 当下拉开关机构启用时，在修改的降压调节器电路内通过下拉开关机构的电流（Vx）或电流被感测到，其中下拉开关机构耦合到电感器的上游端 并且与电容器并联耦合。 计算下拉切换机制被禁用的目标时间（tlf），并且在计算的目标时间下拉下拉晶体管被禁用。

公开(公告)号：US20150205757A1

公开(公告)日：2015-07-23

申请号：US14161628

申请日：2014-01-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G06F17/10

CPC classification number: G06F9/30185 ,  G06F8/437 ,  G06F8/447 ,  G06F9/3001 ,  G06F9/30025

Abstract: A system, method, and computer program product are provided for executing casting-arithmetic instructions. The method comprises receiving a casting-arithmetic instruction that specifies an arithmetic operation to be performed on input data and at least one casting operation of an input casting operation and an output casting operation. Upon determining that the casting-arithmetic instruction specifies the input casting operation, the input casting operation is performed on identified terms comprising the input data. Then the arithmetic operation is performed on the input data to generate an arithmetic result. Upon determining that the casting-arithmetic instruction specifies the output casting operation, the output casting operation is performed on the arithmetic result.

Abstract translation: 提供了一种用于执行铸造算术指令的系统，方法和计算机程序产品。 该方法包括接收指定对输入数据执行的算术运算和输入转换操作和输出转换操作的至少一个投射操作的铸造算术指令。 在确定铸造算术指令指定输入铸造操作时，对包括输入数据的识别项执行输入铸造操作。 然后对输入数据进行算术运算，生成运算结果。 在确定铸造算术指令指定输出转换操作时，对算术结果执行输出转换操作。

公开(公告)号：US09076551B2

公开(公告)日：2015-07-07

申请号：US13933058

申请日：2013-07-01

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  John W. Poulton ,  Thomas Hastings Greer, III

IPC: G11C11/24 ,  G11C11/4096 ,  G11C7/10

CPC classification number: G11C11/4096 ,  G11C7/1057 ,  G11C7/1069

Abstract: A system includes a control circuit and first, second, and third ground-referenced single-ended signaling (GRS) driver circuits that are each coupled to an output signal. The control circuit is configured to generate a first, second, and third set of control signals that are each based on a respective phase of a clock signal. Each GRS driver circuit is configured to pre-charge a capacitor to store a charge based on the respective set of control signals during at least one phase of the clock signal and drive the output signal relative to a ground network by discharging the charge during a respective phase of the clock signal.

Abstract translation: 系统包括控制电路和分别耦合到输出信号的第一，第二和第三接地参考单端信令（GRS）驱动器电路。 控制电路被配置为产生基于时钟信号的相应相位的第一，第二和第三组控制信号。 每个GRS驱动器电路被配置为在时钟信号的至少一个相位期间基于相应的控制信号集来预先充电电容器以存储电荷，并且在相应的时间期间通过放电来驱动输出信号相对于地面网络 时钟信号的相位。