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公开(公告)号：US09886409B2
公开(公告)日：2018-02-06
申请号：US14715394
申请日：2015-05-18
Applicant: NVIDIA Corporation
Inventor： Stephen William Keckler , William J. Dally , Steven Lee Scott , Brucek Kurdo Khailany , Michael Allen Parker
CPC classification number: G06F13/409 , G06F13/1668 , G06F13/4068 , G06F17/5054
Abstract: An integrated circuit device comprises pin resources, a memory controller circuit, a network interface controller circuit, and transmitter circuitry. The pin resources comprise pads coupled to off-chip pins of the integrated circuit device. The memory controller circuit comprises a first interface and the network interface controller circuit comprises a second interface. The transmitter circuitry is configurable to selectively couple either a first signal of the first interface or a second signal of the second interface to a first pad of the pin resources based on a pin distribution between the first interface and the second interface.
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公开(公告)号：US20170212857A1
公开(公告)日：2017-07-27
申请号：US14715394
申请日：2015-05-18
Applicant: NVIDIA Corporation
Inventor： Stephen William Keckler , William J. Dally , Steven Lee Scott , Brucek Kurdo Khailany , Michael Allen Parker
CPC classification number: G06F13/409 , G06F13/1668 , G06F13/4068 , G06F17/5054
Abstract: An integrated circuit device comprises pin resources, a memory controller circuit, a network interface controller circuit, and transmitter circuitry. The pin resources comprise pads coupled to off-chip pins of the integrated circuit device. The memory controller circuit comprises a first interface and the network interface controller circuit comprises a second interface. The transmitter circuitry is configurable to selectively couple either a first signal of the first interface or a second signal of the second interface to a first pad of the pin resources based on a pin distribution between the first interface and the second interface.
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公开(公告)号：US09058453B2
公开(公告)日：2015-06-16
申请号：US13902701
申请日：2013-05-24
Applicant: NVIDIA Corporation
Inventor： Stephen William Keckler , William J. Dally , Steven Lee Scott , Brucek Kurdo Khailany , Michael Allen Parker
IPC: G06F17/50
CPC classification number: G06F13/409 , G06F13/1668 , G06F13/4068 , G06F17/5054
Abstract: A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.
Abstract translation: 提供了一种用于配置多个引脚资源的系统和方法。 该方法包括识别主要专用集成电路（ASIC）设备的多个引脚资源，并且基于第一接口和第二接口之间的引脚分配来配置多个引脚资源，其中第一接口提供第一通信路径 在主ASIC设备和第一设备之间，并且第二接口提供主ASIC设备和第二设备之间的第二通信路径。
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公开(公告)号：US20140351780A1
公开(公告)日：2014-11-27
申请号：US13902701
申请日：2013-05-24
Applicant: Nvidia Corporation
Inventor： Stephen William Keckler , William J. Dally , Steven Lee Scott , Brucek Kurdo Khailany , Michael Allen Parker
IPC: G06F17/50
CPC classification number: G06F13/409 , G06F13/1668 , G06F13/4068 , G06F17/5054
Abstract: A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.
Abstract translation: 提供了一种用于配置多个引脚资源的系统和方法。 该方法包括识别主要专用集成电路（ASIC）设备的多个引脚资源，并且基于第一接口和第二接口之间的引脚分配来配置多个引脚资源，其中第一接口提供第一通信路径 在主ASIC设备和第一设备之间，并且第二接口提供主ASIC设备和第二设备之间的第二通信路径。
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