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1.
公开(公告)号:US20230237671A1
公开(公告)日:2023-07-27
申请号:US17584151
申请日:2022-01-25
Applicant: NVIDIA Corporation
Inventor: Tushar Khinvasara
IPC: G06T7/20 , G06T3/40 , G06V10/22 , G06V10/764
CPC classification number: G06T7/20 , G06T3/40 , G06V10/22 , G06V10/764 , G06T2207/30248 , G06T2200/28
Abstract: Disclosed are apparatuses, systems, and techniques that may perform efficient deployment of machine learning for detection and classification of moving objects in streams of images. A set of machine learning models with different input sizes may be used for parallel processing of various regions of interest in multiple streams of images. Both the machine learning models as well as the inputs into these models may be selected dynamically based on a size of the regions of interest.
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公开(公告)号:US20230281042A1
公开(公告)日:2023-09-07
申请号:US17685277
申请日:2022-03-02
Applicant: NVIDIA Corporation
Inventor: Tushar Khinvasara
CPC classification number: G06F9/5016 , G06N5/04 , G06N3/02
Abstract: Apparatuses, systems, and techniques to allocate memory based on a part of a sequence of items. In at least one embodiment, memory is allocated based on the size of a sliding window used to analyze images with neural networks.
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公开(公告)号:US20230376450A1
公开(公告)日:2023-11-23
申请号:US17944229
申请日:2022-09-14
Applicant: Nvidia Corporation
Inventor: Adit Ranadive , Omri Kahalon , Aviad Shaul Yehezkel , Liran Liss , Gal Shalom , Yorai Itzhak Zack , Tushar Khinvasara
CPC classification number: G06F15/825 , G06F9/3867
Abstract: A method for processing includes receiving a definition of a processing pipeline including multiple sequential processing stages. The processing pipeline is partitioned into a plurality of partitions. The first partition of the processing pipeline is executed on a first computational accelerator, whereby the first computational accelerator writes output data from a final stage of the first partition to an output buffer in a first memory. The output data are copied over a packet communication network to an input buffer in a second memory. The second partition of the processing pipeline is executed on a second computational accelerator using the copied output data in the second memory as input data to a first stage of the second partition.
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公开(公告)号:US20210117859A1
公开(公告)日:2021-04-22
申请号:US17015318
申请日:2020-09-09
Applicant: Nvidia Corporation
Inventor: Philip J. Rogers , Bhanu Pisupati , Tushar Khinvasara , Rajat Chopra , Kaustubh Purandare
Abstract: Resources, such as machine learning models, can be updated for an application without any significant downtime for that application. For an application hosted at a network edge, the application can be deployed in a container and one or more model versions stored in local storage at the edge, which can be mounted into the container as necessary. When a different model version is to be used, a configuration change or new context can be used to trigger the application to automatically change to the different model version. This updating can be performed seamlessly, without any loss of data.
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5.
公开(公告)号:US12211216B2
公开(公告)日:2025-01-28
申请号:US17584151
申请日:2022-01-25
Applicant: NVIDIA Corporation
Inventor: Tushar Khinvasara
IPC: G06T7/20 , G06T3/40 , G06V10/22 , G06V10/764
Abstract: Disclosed are apparatuses, systems, and techniques that may perform efficient deployment of machine learning for detection and classification of moving objects in streams of images. A set of machine learning models with different input sizes may be used for parallel processing of various regions of interest in multiple streams of images. Both the machine learning models as well as the inputs into these models may be selected dynamically based on a size of the regions of interest.
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公开(公告)号:US20240056589A1
公开(公告)日:2024-02-15
申请号:US17884436
申请日:2022-08-09
Applicant: NVIDIA Corporation
Inventor: Jitendra Kumar , Tushar Khinvasara , Bhushan Rupde , Kaustubh Purandare
IPC: H04N19/423 , H04L65/65 , H04L69/22 , H04N19/169 , H04N19/70 , H04N19/436
CPC classification number: H04N19/423 , H04L65/65 , H04L69/22 , H04N19/188 , H04N19/70 , H04N19/436
Abstract: Disclosed are apparatuses, systems, and techniques that improve memory and computational efficiency of remote direct memory accesses into a memory of a graphics processing unit. The techniques include but are not limited to receiving packets with video frame data, storing the plurality of packets in a memory of a network controller, processing the packets to obtain unit(s) of the video frame, storing the unit(s) representative of the video frame in a memory of a graphics processing unit (GPU), and extracting the data of the video frame from the units representative of the video frame, stored in the memory of the GPU, to render the video frame.
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