公开(公告)号：US20230315328A1

公开(公告)日：2023-10-05

申请号：US17698409

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Hemayet HOSSAIN ,  Steven E. MOLNAR ,  Jonathon Stuart Ramsay EVANS ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Vyas VENKATARAMAN ,  Mark HAIRGROVE ,  Geoffrey GERFIN ,  Jeffrey M. SMITH ,  Terje BERGSTROM ,  Vikram SETHI ,  Piyush PATEL

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.

公开(公告)号：US20230021678A1

公开(公告)日：2023-01-26

申请号：US17380424

申请日：2021-07-20

Applicant: NVIDIA CORPORATION

Inventor： Michael Allen PARKER ,  Debajit BHATTACHARYA ,  David FONTAINE ,  Shirish GADRE ,  Wishwesh Anil GANDHI ,  Olivier GIROUX ,  Hemayet HOSSAIN ,  Ronny M. KRASHINSKY ,  Ze LONG ,  Raymond Hoi Man WONG

IPC: G06F9/52 ,  G06F9/30

Abstract: Various embodiments include a parallel processing computer system that provides multiple memory synchronization domains in a single parallel processor to reduce unneeded synchronization operations. During execution, one execution kernel may synchronize with one or more other execution kernels by processing outstanding memory references. The parallel processor tracks memory references for each domain to each portion of local and remote memory. During synchronization, the processor synchronizes the memory references for a specific domain while refraining from synchronizing memory references for other domains. As a result, synchronization operations between kernels complete in a reduced amount of time relative to prior approaches.

公开(公告)号：US20140122809A1

公开(公告)日：2014-05-01

申请号：US13664387

申请日：2012-10-30

Applicant: NVIDIA CORPORATION

Inventor： James Patrick ROBERTSON ,  Gregory Alan MUTHLER ,  Hemayet HOSSAIN ,  Timothy John PURCELL ,  Karan MEHRA ,  Peter B. HOLMQVIST ,  George R. LYNCH

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/084 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0895

Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty. The technique further involves determining whether a total number of cache lines marked as dirty in the set of cache lines is less than, equal to, or greater than a first threshold value, and: not transmitting a dirty data notification to the frame buffer logic when the total number is less than the threshold value, or transmitting a dirty data notification to the frame buffer logic when the total number is equal to or greater than the first threshold value.

Abstract translation: 本发明的一个实施例提出了一种用于处理来自一个或多个客户端的中间缓存所接收的命令的技术。 该技术涉及从仲裁器单元接收第一写入命令，其中第一写入命令指定第一存储器地址，确定与中间缓存中包括的一组高速缓存行相关联的第一高速缓存行与第一存储器地址相关联， 使得与第一写命令相关联的数据被写入第一高速缓存行，并将第一高速缓存行标记为脏。 该技术还涉及确定在该组高速缓存行中标记为脏的总数量是否小于，等于或大于第一阈值，以及：不将脏数据通知发送到帧缓冲器逻辑，当 总数小于阈值，或者当总数等于或大于第一阈值时，将脏数据通知发送到帧缓冲器逻辑。