公开(公告)号：US09509306B2

公开(公告)日：2016-11-29

申请号：US13866864

申请日：2013-04-19

Applicant: NXP B.V.

Inventor： Soenke Ostertun ,  Michael Ziesmann

IPC: H03K19/003 ,  H01L23/00 ,  H01L21/306

CPC classification number: H03K19/003 ,  H01L21/306 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.

Abstract translation: 根据本发明的一个方面，构思了一种集成电路，其包括至少部分地在所述集成电路的钝化层中实现的物理不可克隆功能。 根据本发明的另一方面，构思了用于制造集成电路的相应方法。 根据本发明的另一方面，构思了包括所述类型的集成电路的电子设备。

公开(公告)号：US08860230B2

公开(公告)日：2014-10-14

申请号：US13961129

申请日：2013-08-07

Applicant: NXP B.V.

Inventor： Florian Schmitt ,  Michael Ziesmann

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02372 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the passivation layer and electrically coupled to the circuit. A wire is formed on the passivation layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.

Abstract translation: 在一个实施例中，提供了一种半导体，其包括基板和形成在基板上的多个布线层和电介质层，布线层实现电路。 电介质层分离多个布线层中的相邻布线层。 在多个布线层上形成第一钝化层。 第一接触焊盘形成在钝化层中并电耦合到电路。 导线形成在钝化层上并连接到接触垫。 通过硅衬底，多个布线和电介质层以及钝化层形成贯通硅通孔（TSV）。 TSV与形成在钝化层上的导线电连接。 除了由形成在钝化层上的金属线提供的连接之外，TSV与布线层电隔离。

公开(公告)号：US20130307578A1

公开(公告)日：2013-11-21

申请号：US13866864

申请日：2013-04-19

Applicant: NXP B.V.

Inventor： Soenke Ostertun ,  Michael Ziesmann

IPC: H03K19/003 ,  H01L21/306

CPC classification number: H03K19/003 ,  H01L21/306 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.

Abstract translation: 根据本发明的一个方面，构思了一种集成电路，其包括至少部分地在所述集成电路的钝化层中实现的物理不可克隆功能。 根据本发明的另一方面，构思了用于制造集成电路的相应方法。 根据本发明的另一方面，构思了包括所述类型的集成电路的电子设备。