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公开(公告)号：US20230315325A1
公开(公告)日：2023-10-05
申请号：US17711968
申请日：2022-04-01
Applicant: NXP B.V.
Inventor： Soenke Ostertun
IPC: G06F3/06
CPC classification number: G06F3/065 , G06F3/0679 , G06F3/0616 , G06F3/0658
Abstract: A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.
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2.发明公开公开(公告)号：US20230274787A1
公开(公告)日：2023-08-31
申请号：US18313669
申请日：2023-05-08
Applicant: NXP B.V.
Inventor： Soenke Ostertun , Björn Fay , Vitaly Ocheretny
CPC classification number: G11C29/42 , G06F11/1056 , G06F11/1068 , G06F11/1096
Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.
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公开(公告)号：US20140089612A1
公开(公告)日：2014-03-27
申请号：US14029659
申请日：2013-09-17
Applicant: NXP B.V.
Inventor： Martin Feldhofer , Franz Amtmann , Soenke Ostertun , Alicia da Conceicao
IPC: G06F12/00
CPC classification number: G06F12/00 , H03K21/403
Abstract: An electronic counter comprising a sequence of memory cells, each memory cell being non-volatile and supporting a one state and a zero state, the counter being configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter, the increment logic comprising programming increment logic and erasing increment logic, the increment logic being configured to alternate between a programming phase in which the programming increment logic advances the pattern, and an erasing phase in which the erasing increment logic advances the pattern, wherein the programming increment logic is configured to program a next cell of the sequence of non-volatile memory cells from a zero state to a one state, the program phase terminating when all memory cells of the sequence of memory cells are in the one state, the erasing increment logic is configured to erase a next cell of the sequence of non-volatile memory cells from a one state to a zero state, the erase phase terminating when all memory cells of the sequence of memory cells are in the zero state.
Abstract translation: 一种包括存储器单元序列的电子计数器，每个存储单元是非易失性的并且支持一种状态和零状态，所述计数器被配置为将计数器的当前计数状态的至少一部分表示为一种模式 以及存储器单元序列的存储器单元中的零状态，以及被配置为将一个和零个状态的模式推进到下一个模式以表示计数器的增量的递增逻辑，该增量逻辑包括编程增量逻辑和擦除增量逻辑 所述增量逻辑被配置为在所述编程增量逻辑推进所述模式的编程阶段与所述擦除增量逻辑使所述模式前进的擦除阶段之间交替，其中所述编程增量逻辑被配置为对 非易失性存储单元的序列从零状态到一状态，程序阶段在序列的所有存储单元时终止 所述擦除增量逻辑被配置为将所述非易失性存储器单元序列的下一个单元从一个状态擦除到零状态，所述擦除阶段在所述存储器单元的序列的所有存储单元 存储单元处于零状态。
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公开(公告)号：US20140068762A1
公开(公告)日：2014-03-06
申请号：US14010145
申请日：2013-08-26
Applicant: NXP B.V.
Inventor： Soenke Ostertun , Joachim Christoph Hans Garbe
IPC: G06F21/60
CPC classification number: G06F21/60 , G06K19/07372
Abstract: There is provided a detection arrangement for detecting an attack to internal signals in a semiconductor device. The detection arrangement comprises a first input terminal, a second input terminal, and a comparison unit. The first input terminal is adapted to receive a first signal being indicative for a signal at a first stage of a driver of the semiconductor device, the driver being capable to drive signals internally to the semiconductor device. The second input terminal is adapted to receive a second signal being indicative for a signal at a second stage of the driver of the semiconductor device. The comparison unit is adapted to compare the first signal and the second signal and to determine a time period during which the signals are equal, wherein the determined time period is indicative for a potential attack, if the determined time period is above a predefined threshold.
Abstract translation: 提供了用于检测对半导体器件中的内部信号的攻击的检测装置。 检测装置包括第一输入端子，第二输入端子和比较单元。 第一输入端子适于接收指示半导体器件的驱动器的第一级处的信号的第一信号，该驱动器能够在半导体器件内部驱动信号。 第二输入端子适于接收在半导体器件的驱动器的第二级指示信号的第二信号。 所述比较单元适于比较所述第一信号和所述第二信号，并且确定所述信号相等的时间段，其中如果所确定的时间段高于预定阈值，则确定的时间段指示潜在的攻击。
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公开(公告)号：US09866206B2
公开(公告)日：2018-01-09
申请号：US15186408
申请日：2016-06-17
Applicant: NXP B.V.
Inventor： Maurits Storms , Soenke Ostertun , Frantisek Cevela
CPC classification number: H03K3/356182 , G11C5/14 , G11C5/147 , G11C8/08 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , H02M3/07 , H03K3/35613
Abstract: There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply terminal (122), a second voltage supply terminal (124), and a first biasing voltage output terminal (126), wherein the first switching element (N11, N12) is adapted to connect the first biasing voltage output terminal (126) to the first voltage supply terminal (122) in dependency of the voltage at the first latch output terminal (114), and wherein the second switching element (N13) is adapted to connect the first biasing voltage output terminal (126) to the second voltage supply terminal (124) in dependency of the voltage at the second latch output terminal (115), and (c) a second output stage (130) comprising a third switching element (N21), a fourth switching element (N22), a third voltage supply terminal (132), a fourth voltage supply terminal (134), and a second biasing voltage output terminal (136), wherein the third switching element (N21) is adapted to connect the second biasing voltage output terminal (136) to the third voltage supply terminal (132) in dependency of the voltage at the first latch output terminal (114), and wherein the fourth switching element (N22) is adapted to connect the second biasing voltage output terminal (136) to the fourth voltage supply terminal (134) in dependency of the voltage at the second latch output terminal (115).There is also described a memory system and a method of operating the driver circuit.
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Patent Agency Ranking
公开(公告)号：US12154643B2
公开(公告)日：2024-11-26
申请号：US18084704
申请日：2022-12-20
Applicant: NXP B.V.
Inventor： Soenke Ostertun
Abstract: In a non-volatile memory (NVM) system of a memory device, a memory controller connected to memory cell arrays of the NVM system is configured to perform the steps of selecting a memory cell to test, energizing a test circuit connected to the memory cell under a first biasing condition, reading a measurement of an electrical property of the memory cell, and determining, based on the measurement, whether the memory cell is formed or unformed. In embodiments, the system and method include protecting the test circuit from attack by validating the results of the testing. The memory controller is further configured to energize the test circuit under a second biasing condition that produces a known test result whether the memory cell is formed or unformed; if the result of the second test is not the expected result, the memory controller determines that the testing circuit is malfunctioning or under attack.
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7.发明授权公开(公告)号：US12040034B2
公开(公告)日：2024-07-16
申请号：US18313669
申请日：2023-05-08
Applicant: NXP B.V.
Inventor： Soenke Ostertun , Björn Fay , Vitaly Ocheretny
CPC classification number: G11C29/42 , G06F11/1056 , G06F11/1068 , G06F11/1096
Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.
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公开(公告)号：US20160373092A1
公开(公告)日：2016-12-22
申请号：US15186408
申请日：2016-06-17
Applicant: NXP B.V.
Inventor： Maurits Storms , Soenke Ostertun , Frantisek Cevela
CPC classification number: H03K3/356182 , G11C5/14 , G11C5/147 , G11C8/08 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , H02M3/07 , H03K3/35613
Abstract: There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply terminal (122), a second voltage supply terminal (124), and a first biasing voltage output terminal (126), wherein the first switching element (N11, N12) is adapted to connect the first biasing voltage output terminal (126) to the first voltage supply terminal (122) in dependency of the voltage at the first latch output terminal (114), and wherein the second switching element (N13) is adapted to connect the first biasing voltage output terminal (126) to the second voltage supply terminal (124) in dependency of the voltage at the second latch output terminal (115), and (c) a second output stage (130) comprising a third switching element (N21), a fourth switching element (N22), a third voltage supply terminal (132), a fourth voltage supply terminal (134), and a second biasing voltage output terminal (136), wherein the third switching element (N21) is adapted to connect the second biasing voltage output terminal (136) to the third voltage supply terminal (132) in dependency of the voltage at the first latch output terminal (114), and wherein the fourth switching element (N22) is adapted to connect the second biasing voltage output terminal (136) to the fourth voltage supply terminal (134) in dependency of the voltage at the second latch output terminal (115).There is also described a memory system and a method of operating the driver circuit.
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公开(公告)号：US20130307578A1
公开(公告)日：2013-11-21
申请号：US13866864
申请日：2013-04-19
Applicant: NXP B.V.
Inventor： Soenke Ostertun , Michael Ziesmann
IPC: H03K19/003 , H01L21/306
CPC classification number: H03K19/003 , H01L21/306 , H01L23/576 , H01L2924/0002 , H01L2924/00
Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.
Abstract translation: 根据本发明的一个方面，构思了一种集成电路，其包括至少部分地在所述集成电路的钝化层中实现的物理不可克隆功能。 根据本发明的另一方面，构思了用于制造集成电路的相应方法。 根据本发明的另一方面，构思了包括所述类型的集成电路的电子设备。
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公开(公告)号：US20240203518A1
公开(公告)日：2024-06-20
申请号：US18084704
申请日：2022-12-20
Applicant: NXP B.V.
Inventor： Soenke Ostertun
CPC classification number: G11C29/46 , G11C7/24 , G11C29/40 , G11C2029/1204
Abstract: In a non-volatile memory (NVM) system of a memory device, a memory controller connected to memory cell arrays of the NVM system is configured to perform the steps of selecting a memory cell to test, energizing a test circuit connected to the memory cell under a first biasing condition, reading a measurement of an electrical property of the memory cell, and determining, based on the measurement, whether the memory cell is formed or unformed. In embodiments, the system and method include protecting the test circuit from attack by validating the results of the testing. The memory controller is further configured to energize the test circuit under a second biasing condition that produces a known test result whether the memory cell is formed or unformed; if the result of the second test is not the expected result, the memory controller determines that the testing circuit is malfunctioning or under attack.
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