公开(公告)号：US09666667B2

公开(公告)日：2017-05-30

申请号：US14714124

申请日：2015-05-15

Applicant: NXP B.V.

Inventor： Peter Steeneken ,  Anco Heringa ,  Radu Surdeanu ,  Luc Van Dijk ,  Hendrik Johannes Bergveld

IPC: H02M7/537 ,  H01L29/06 ,  H01L29/417 ,  H02M5/00 ,  H02M3/00 ,  H03K17/687 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/4238 ,  H02M3/00 ,  H02M5/00 ,  H02M7/537 ,  H03K17/687

Abstract: Aspects of the present disclosure are directed toward apparatuses, methods, and systems that include at least two regions of a first semiconductor material and at least two regions of second semiconductor material that are alternatively interleaved. Additionally, the apparatuses, methods, and systems include a first electrode and a second electrode that can operate both as a source and drain. The apparatuses, methods, and systems also include a first gate electrode having multiple portions on the first semiconductor material and a second gate electrode having multiple portions on the second semiconductor material that bidirectionally control current flow between the first electrode and the second electrode.

公开(公告)号：US20160043708A1

公开(公告)日：2016-02-11

申请号：US14802840

申请日：2015-07-17

Applicant: NXP B.V.

Inventor： Anco Heringa ,  Erwin Hijzen ,  Radu Surdeanu

IPC: H03K5/24 ,  H01L29/08 ,  H03K17/687 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/78 ,  H01L29/45

CPC classification number: H03K5/2472 ,  H01L23/5226 ,  H01L23/53271 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/404 ,  H01L29/45 ,  H01L29/7816 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/7836 ,  H01L2924/0002 ,  H03K17/6871 ,  H01L2924/00

Abstract: A semiconductor device comprising: a substrate having: a first terminal region; a second terminal region; a first extension region that extends from the first terminal region towards the second terminal region; a second extension region that extends from the second terminal region towards the first terminal region; a channel region between the first and second extension regions; a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region; a first control conductor that overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and a second control conductor that overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region, wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conductor.

Abstract translation: 一种半导体器件，包括：衬底，具有：第一端子区域; 第二终端区域; 从所述第一端子区域朝向所述第二端子区域延伸的第一延伸区域; 从所述第二端子区域朝向所述第一端子区域延伸的第二延伸区域; 第一和第二延伸区域之间的沟道区域; 栅极导体，其覆盖在所述衬底的沟道区域上，所述栅极导体被配置为控制所述沟道区域中的导通; 第一控制导体，其覆盖在第一延伸区域的至少一部分上，第一控制导体被配置为控制第一延伸区域中的导通; 以及第二控制导体，其覆盖在所述第二延伸区域的至少一部分上，所述第二控制导体被配置为控制所述第二延伸区域中的导通，其中所述第一和第二控制导体在所述半导体器件内与所述栅极导体电隔离。